Memory Decoding Architecture With Shared Word Line Electrodes
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Solution Overview
Problem
Existing memory devices face challenges in efficiently accessing and decoding data from memory cells, leading to limitations in access operation speed and data throughput due to the large footprint required by decoding circuitry.
Innovation Solution
The proposed decoding architecture involves sharing electrodes between two word line plates in the same plane, allowing for parallel access of memory cells through a pillar tile that is larger than individual word line tiles, reducing the footprint of pillar decoders and enabling concurrent access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If decoding circuitry is implemented with separate electrodes for each word line plate, then decoding accuracy is improved, but the footprint area increases
Solution Approach 1:
The patent combines decoding functionality for multiple word line plates into shared electrodes. Specifically, a first electrode is shared between a first word line plate and a second word line plate, and a second electrode is shared between a third word line plate and a fourth word line plate. This merging approach reduces the total number of electrodes required, thereby reducing the footprint area while maintaining decoding capability across all word line plates.
Solution Approach 2:
The shared electrodes serve multiple functions by being coupled to multiple word line plates simultaneously. Each shared electrode can selectively activate different word line plates based on decoding requirements, making the electrode structure universal and multi-functional. This eliminates the need for dedicated electrodes for each word line plate, reducing overall circuitry footprint.
2Productivity
If more decoding circuitry is added to access more memory cells in parallel, then data throughput is improved, but the device complexity increases
Solution Approach 1:
The patent merges decoding operations for multiple word line plates into shared electrode structures. By combining the electrode resources, the system can access multiple memory cells in parallel through coordinated activation of shared electrodes, improving data throughput without proportionally increasing circuitry complexity.
Solution Approach 2:
The patent introduces a new dimensional organization by arranging word line plates and shared electrodes in a multi-plane three-dimensional structure. This spatial reorganization allows parallel access operations across different planes and layers, enabling increased throughput without linearly increasing the complexity of the decoding circuitry in any single plane.
Data Source
AI summary
Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Two word line plates in a same plane may be activated via a shared electrode. Memory cells coupled with the two word line plates sharing the electrode, or a subset thereof, may represent a logical page for accessing memory cells. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.