Semiconductor Memory Decoding Signal Routing for Speed
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Solution Overview
Problem
Conventional semiconductor memory devices face a heavy load on decoding signals due to their connection to a large number of sub-word line drivers, which decreases the operational speed of the device.
Innovation Solution
The semiconductor memory device is designed such that each decoding signal is connected to fewer sub-word line drivers, with decoding signal generators activated in accordance with address signals and communicating solely in the word line direction, reducing the load on each decoding signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If each decoding signal is connected to a large number of sub-word line drivers, then the decoding signals can drive more word lines, but the load on each decoding signal increases and operational speed decreases
Solution Approach 1:
The patent divides the semiconductor memory device into multiple sub-arrays, with each sub-array having its own dedicated decoding signal generators. This segmentation ensures that each decoding signal only needs to drive a limited number of sub-word line drivers within its own sub-array, reducing the load while maintaining the ability to drive word lines across the entire memory device through hierarchical decoding structures.
2Adaptability or versatility
If each decoding signal is connected to more sub-word line drivers, then more word lines can be controlled, but current consumption increases
Solution Approach 1:
The memory device is segmented into multiple sub-arrays, each with dedicated decoding signal generators. This segmentation limits the number of sub-word line drivers that each decoding signal must drive, thereby reducing the total current consumption while maintaining comprehensive word line control capability through the hierarchical decoding architecture.
3Speed
If decoding signals are connected to fewer sub-word line drivers, then the load on decoding signals decreases and speed improves, but the number of word lines that can be driven is reduced
Solution Approach 1:
The patent employs a hierarchical decoding structure where decoding signal generators in one sub-array can universally control word lines across multiple sub-arrays through shared decoding signals. This multi-functionality allows each decoding signal to drive fewer immediate sub-word line drivers while still achieving comprehensive coverage of all word lines in the memory device through the hierarchical decoding tree.
Data Source
AI summary
A semiconductor memory device comprising decoding signals communicated solely in a word line direction is provided. The semiconductor memory device comprises a sub-array comprising a plurality of memory cells, a plurality of enable signal generators adapted to generate word line enable signals, a plurality of decoding signal generators adapted to generate decoding signals, a plurality of inverted decoding signal generators adapted to generate inverted decoding signals, and a word line driver area comprising a plurality of sub-word line drivers. Each sub-word line driver is adapted to drive a word line in accordance with one of the word line enable signals and a pair of first signals comprising one of the decoding signals and one of the inverted decoding signals. The word line enable signals and the decoding signals are communicated to the sub-word line drivers solely in a word line direction.