Unified Memory Decoding for Test Accuracy
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Solution Overview
Problem
In memory chip testing, the frequent switching between normal and redundant storage unit tests increases testing time and introduces human error due to differences in decoding modes and timing controls, leading to decreased accuracy and efficiency.
Innovation Solution
A memory system with an input module, control module, and selection module that allows for flexible decoding selection without changing the signal input interface, using a decoding selection instruction to perform redundant or normal decoding, ensuring consistent address signal paths and timings, thereby reducing human errors and improving test accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If normal storage units and redundant storage units are tested separately using different test paths and timing controls, then each storage unit type can be tested with its specific decoding mode, but the testing time increases and human test errors increase due to frequent switching
Solution Approach 1:
The patent merges the testing of normal storage units and redundant storage units into a single unified test path. The address input interface and timing control are unified, allowing both storage unit types to be tested sequentially without switching between different test paths. This eliminates the time loss and human errors associated with frequent switching while maintaining the ability to test each storage unit type with its appropriate decoding mode.
Solution Approach 2:
The patent creates a universal test path that can handle both normal storage unit testing and redundant storage unit testing. The address input interface and timing control are designed to be multi-functional, supporting both test modes through a single unified interface. This universality allows the system to adapt to different decoding modes without requiring separate specialized test paths.
2Adaptability or versatility
If normal storage units and redundant storage units are tested separately with different decoding modes, then each storage unit can be accessed through its corresponding address, but frequent switching between tests increases testing time and introduces human error
Solution Approach 1:
The patent implements a universal address input interface that can accommodate both normal decoding mode and redundant decoding mode through a single unified path. The timing control is similarly designed to be multi-functional, supporting both test modes without requiring separate control mechanisms. This reduces operational complexity while preserving the ability to adapt to different decoding requirements.
Solution Approach 2:
The patent introduces dynamic switching capability within the unified test path, allowing the system to flexibly transition between normal decoding mode and redundant decoding mode based on the test requirements. The address input interface and timing control can dynamically adapt to the current test mode without requiring physical reconfiguration or separate dedicated paths for each mode.
Data Source
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AI summary
A memory and an addressing method therefor. The memory comprises: an input module for receiving an address/command input signal at least containing an access address, a command and a decoding selection instruction; a storage array, comprising a plurality of storage blocks, each storage block comprising a plurality of storage units arranged in an array; and a control module, comprising a plurality of storage block local control units, the storage block local control units being respectively connected to the storage blocks, and each storage block local control unit comprising: at least one decoding unit, for performing redundancy decoding or normal decoding on the address/command input signal, an input end of the decoding unit being coupled to the input module, and an output end of the decoding unit being coupled to the storage unit; and a selection module having an input end coupled to the input module and an output end coupled to the decoding unit. The addressing efficiency of the described memory is improved.