3D Memory Array Decoding With TFT Interconnects and Deck Selection
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Solution Overview
Problem
The challenge of increasing memory cell density and reducing the size of CMOS circuitry in 3D memory devices while maintaining efficient decoding and access operations is not adequately addressed by existing technologies.
Innovation Solution
The use of thin film transistors (TFTs) within array layers to facilitate decoding and select/deactivate memory cell decks, offloading some decoding functions from CMOS circuitry, and constructing multiple decks concurrently with array electrodes using a pattern of vias, thereby reducing the CMOS circuitry footprint and current requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased in 3D memory devices, then storage capacity is improved, but CMOS circuitry size and current requirements increase
Solution Approach 1:
The patent segments the decoding function into two parts: CMOS circuitry performs initial address decoding to select specific decks, while TFTs within the array layers perform secondary decoding to select specific memory cells within those decks. This segmentation allows the CMOS circuitry to remain compact while supporting high-density memory arrays through the distributed TFT decoding capability.
Solution Approach 2:
The patent transitions from traditional planar decoding to a three-dimensional decoding architecture where TFTs are embedded within array layers at multiple vertical levels. This dimensional transition enables parallel decoding operations across multiple decks simultaneously, reducing the footprint requirement for CMOS circuitry while supporting increased memory cell density.
2Quantity of substance
If memory cell density is increased in 3D memory devices, then storage capacity is improved, but current requirements for CMOS circuitry increase
Solution Approach 1:
The patent segments the current-consuming decoding operation into two stages: CMOS circuitry consumes current for initial deck selection, while TFTs consume current for secondary cell selection within decks. This segmentation distributes the current load, preventing excessive current demands on the CMOS circuitry even as memory cell density increases.
Solution Approach 2:
The TFTs act as intermediary devices between the CMOS circuitry and the memory cells. They receive control signals from the CMOS circuitry and amplify/condition the signals locally within the array layers, reducing the current burden on the CMOS circuitry while maintaining effective control over high-density memory cells.
3Area of stationary object
If CMOS circuitry size is reduced, then device integration is improved, but decoding functionality may be compromised
Solution Approach 1:
The patent segments the decoding functionality between CMOS circuitry and TFTs, with each performing a portion of the overall decoding task. The CMOS circuitry handles initial address parsing and deck selection, while TFTs handle subsequent cell selection within decks. This segmentation preserves complete decoding capability while allowing the CMOS circuitry footprint to be minimized.
Solution Approach 2:
The TFTs within the array layers provide self-service decoding functionality, performing address decoding locally without requiring external CMOS circuitry support. This self-service capability enables the CMOS circuitry to be minimized while maintaining full decoding versatility through the autonomous TFT decoding operations within the array layers.
Data Source
AI summary
Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.