3D Memory Array Decoding With TFT Interconnects for Multi-Deck Access
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Solution Overview
Problem
Existing memory devices face challenges in increasing memory cell density and reducing manufacturing costs while managing the size of CMOS circuitry required for decoding multiple decks of memory cells in 3D integration, leading to increased substrate area occupation and current requirements.
Innovation Solution
The fabrication of thin film transistors (TFTs) within array layers of a 3D memory device, coupled with CMOS circuitry, to selectively activate or inhibit memory decks, reducing the need for large CMOS circuitry and mitigating parasitic components, while allowing concurrent construction of multiple decks and array electrodes using via patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple decks of memory cells are integrated in 3D to increase memory cell density, then memory cell density is improved, but the substrate area occupied by CMOS circuitry for decoding increases
Solution Approach 1:
The patent transitions from planar 2D memory organization to three-dimensional stacking with multiple decks of memory cells vertically arranged above the substrate. This dimensional change allows increased memory capacity without proportionally increasing the substrate footprint, as memory cells are distributed across multiple vertical layers (decks) that share common bit lines and word lines.
Solution Approach 2:
The CMOS circuitry is designed to universally decode addresses for multiple decks of memory cells using shared bit lines and word lines. The same interconnect structures serve multiple decks simultaneously, reducing the need for dedicated circuitry for each deck and thereby minimizing the total substrate area occupied by decoding circuitry while supporting increased memory density.
2Quantity of substance
If multiple decks of memory cells are integrated in 3D to increase memory cell density, then memory cell density is improved, but the current requirements for CMOS circuitry increase
Solution Approach 1:
The memory array is segmented into multiple independent decks, each accessible through shared interconnects. The row decoder selectively activates specific word lines for specific decks, and the column decoder selectively activates specific bit lines for specific decks. This segmentation allows the CMOS circuitry to handle multiple decks through controlled signal distribution, managing current requirements by activating only the necessary interconnects for the targeted deck rather than requiring full current drive capacity for all decks simultaneously.
Solution Approach 2:
The patent introduces intermediate decoding circuitry (row decoder and column decoder) that acts as a mediator between the CMOS control logic and the multiple memory decks. These decoders translate address signals into selective activation of specific word lines and bit lines for the targeted deck, thereby managing current distribution efficiently and reducing the overall current requirements compared to direct control of all decks.
3Productivity
If via patterns are used to concurrently construct multiple decks and array electrodes, then manufacturing efficiency is improved, but process complexity increases
Solution Approach 1:
The via patterns are designed and formed in advance during the fabrication process to concurrently define the structures for multiple decks and array electrodes. The via holes are patterned through the substrate and dielectric layers before subsequent filling and planarization steps, allowing multiple interconnect structures to be established simultaneously through a single patterning operation, thereby improving manufacturing efficiency despite the increased pattern complexity.
Solution Approach 2:
The fabrication process merges the construction of multiple decks and array electrodes into a single concurrent process using shared via patterns. The same via structures serve dual purposes: forming electrical connections for array electrodes and defining the vertical alignment for multiple memory decks. This merging of construction steps reduces the total number of discrete fabrication operations required, improving manufacturing efficiency while managing process complexity through integrated design.
Data Source
AI summary
Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.