3D Memory Array Decoding With TFT Deck Selection
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Solution Overview
Problem
The challenge in increasing memory cell density in three-dimensional memory devices while minimizing the size of complementary metal oxide semiconductor (CMOS) circuitry, which offsets the benefits of 3D integration, and the need for efficient fabrication techniques to construct thin film transistors (TFTs) within array layers to support multiple decks of memory cells without increasing substrate area.
Innovation Solution
The use of TFTs within array layers to select or inhibit decks of memory cells, coupled with CMOS circuitry, to reduce the area occupied by CMOS circuitry and mitigate parasitic components, along with flexible fabrication techniques that allow concurrent construction of multiple decks and array electrodes using a pattern of vias, optimizing process steps to reduce thermal impacts and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more memory cells are integrated per unit area in three-dimensional memory devices, then memory cell density increases, but the area occupied by CMOS circuitry increases, offsetting the benefits of 3D integration
Solution Approach 1:
The patent divides the decoding function into two parts: CMOS circuitry performs partial decoding to generate row and column addresses, while TFTs perform the remaining decoding by selecting specific memory decks. This segmentation allows CMOS area to remain small while achieving high memory cell density through the added TFT-based deck selection capability.
Solution Approach 2:
Thin film transistors (TFTs) are introduced as intermediary components between the CMOS circuitry and the memory decks. The TFTs act as deck select transistors that receive control signals from CMOS and enable selective access to multiple decks, thereby multiplying memory capacity without proportionally increasing CMOS area.
2Quantity of substance
If thin film transistors are constructed within array layers to support multiple decks, then memory cell density increases, but fabrication complexity increases
Solution Approach 1:
The patent merges the construction of TFTs with the existing array layer fabrication process. TFTs are formed within the same array layers that contain memory cells, using similar material deposition and patterning steps. This integration allows both memory cells and TFTs to be manufactured concurrently without requiring separate fabrication sequences.
Solution Approach 2:
The array layers serve multiple functions: they contain both memory cells and TFTs, and provide both data storage and deck selection capabilities. The same fabrication processes that create memory cell structures also create TFT structures, making the fabrication system universally capable of producing both component types.
3Manufacturing precision
If conventional fabrication techniques are used to construct TFTs and memory cells separately, then manufacturing precision is maintained, but productivity decreases
Solution Approach 1:
The patent performs preliminary actions by preparing the array layer structure and material stacks in advance, before the final patterning step that defines both TFT and memory cell geometries. The material layers are deposited and preliminary patterns are formed, then a single subsequent etching step completes both TFT and memory cell structures simultaneously, maintaining precision while doubling productivity.
Data Source
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AI summary
Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.