Semiconductor Memory Decoding Using Iterative Soft-Bit Voltage Sets

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Solution Overview

Problem

Semiconductor memory devices face challenges in reliable data reading due to manufacturing variations and threshold voltage distributions, leading to low reliability at voltage limits in hard-decision decoding, while soft-decision decoding requires multiple voltages for accurate probability-based decoding, increasing complexity and power consumption.

Innovation Solution

A semiconductor memory device and method that uses a word line controlling section to apply specific voltage sets for hard and soft bit reading, coupled with a log likelihood ratio table for soft-decision decoding, allowing iterative calculation based on probability to improve data reliability and decoding efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If hard-decision decoding is used with threshold voltage reading, then device complexity is reduced, but data reliability deteriorates due to manufacturing variations and threshold voltage distributions

Engineering Contradiction:
Improvedecoding complexityVSAvoiddata reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent changes the parameter of read voltage from a single threshold voltage to multiple intermediate voltages (e.g., V1 to V4) that are higher and lower than the threshold voltage. This allows the system to read multiple soft bit values (e.g., +2, +1, 0, -1, -2) that represent different probability levels, thereby improving data reliability while maintaining manageable decoding complexity through iterative calculation based on probability.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If soft-decision decoding with multiple intermediate voltages is applied, then data reliability is improved, but device complexity and power consumption increase

Engineering Contradiction:
Improvedata reliabilityVSAvoiddecoding complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the decoding process into iterative calculation steps that process multiple soft bit values separately. By dividing the decoding into manageable iterations using probability-based calculations, the system handles the complexity of multiple intermediate voltages in a structured way, making the decoding process more tractable while maintaining high data reliability.

Inventive Principle:
Principle #1Segmentation

3Reliability

If soft-decision decoding with multiple intermediate voltages is applied, then data reliability is improved, but power consumption increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies partial action by selectively applying intermediate voltages based on the specific memory cell and data requirements. Instead of uniformly applying all intermediate voltages to all memory cells, the system optimizes voltage application to achieve the necessary probability-based decoding information, thereby reducing overall power consumption while maintaining improved data reliability.

Inventive Principle:
Principle #16Partial or excessive action

4Quantity of substance

If multiple voltage sets are applied for multi-level memory cells, then storage density is improved, but the number of required read voltages increases

Engineering Contradiction:
Improvestorage densityVSAvoidnumber of read voltages
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent makes the intermediate voltage sets universal by designing them to serve multiple functions across different memory cells and data bits. The same set of intermediate voltages (V1 to V4) is used to read multiple soft bit values from each memory cell, enabling multi-level storage (e.g., 2N bits per cell) without proportionally increasing the number of distinct voltage levels required, thus managing complexity while improving storage density.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8385117B2Semiconductor memory device and decoding method
Publication Date: 2013.02.26 KIOXIA CORP
  • US8385117B2 patent drawing
  • US8385117B2 patent drawing
  • US8385117B2 patent drawing

AI summary

A memory card decodes three bits of data stored in one memory cell and belonging to different pages, each being a unit of reading, by iterative calculation using probability based on eight threshold voltage distributions. The memory card includes a word line controlling section configured to select one required to read 1-bit data belonging to one of the pages to be read from among seven voltage sets which are composed of seven reference voltages for hard bit reading and a plurality of intermediate voltages for soft bit reading and perform control to apply the voltages of the selected voltage set as read voltages to the memory cell, a log likelihood ratio table storing section, and a decoder configured to decode read data using a log likelihood ratio.