Memory Deep Power-Down State Component Control
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Solution Overview
Problem
Flash memory applications face challenges in extending battery life and reducing power consumption, especially in devices that require frequent battery replacement or charging, due to high power usage.
Innovation Solution
A memory system with operational states including a deep power-down state that disables unnecessary components, allowing the memory to enter a higher power state only when needed, thereby reducing power consumption by enabling only essential components during active usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the memory operates in a higher power state to enable full functionality, then operational capability is improved, but power consumption increases
Solution Approach 1:
The memory device dynamically transitions between multiple operational states (deep power-down state, power-down state, and standby state) based on operational requirements. The controller enables or disables different internal components (memory cell array, instruction decoder, controller) according to the current state, allowing the system to adapt its power consumption and functionality dynamically rather than operating in a fixed high-power mode.
Solution Approach 2:
The patent changes the operational parameters of the memory device by introducing multiple power states with different enablement configurations. By transitioning between deep power-down state (all components disabled), power-down state (instruction decoder enabled), and standby state (all components enabled), the system adjusts its power consumption parameter while maintaining the ability to provide full functionality when needed.
2Use of energy by moving object
If the memory enters deep power-down state to reduce power consumption, then power consumption is reduced, but response time to become operational increases
Solution Approach 1:
The patent segments the power-down process into distinct states with different levels of component enablement. Instead of a single power-down state, there are two levels: deep power-down state (all components disabled for maximum power saving) and power-down state (instruction decoder enabled for faster response). This segmentation allows the system to choose the appropriate state based on whether minimal or moderate power consumption is required, balancing power savings with response time requirements.
Data Source
AI summary
A memory, a method controlling method and a system are disclosed. The memory includes: an array of memory cells; an instruction decoder; a controller; and an I/O interface, including a chip select pin. The operational states of the memory include a deep power-down state, and in the deep power-down state, they are all disabled. In response to receiving a chip select signal, the memory enters a higher power state from the deep power-down state. The memory of the present disclosure provides the deep power-down state that disables the decoder, and the memory in the deep power-down state exits directly to a higher power state to achieve some functions without enabling all components, thereby reducing power consumption.