Semiconductor Memory Defect Detection via Selection Transistor Control
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Solution Overview
Problem
Semiconductor memory devices face defects due to short circuits between conducting layers and semiconductor layers, leading to malfunction during write and read operations, which are not efficiently detected in existing technologies.
Innovation Solution
A defect detection method that involves supplying specific voltages to selection transistors and detecting voltages or currents in the memory cell array using a sense amplifier to identify short circuits, allowing for the identification and recording of defective blocks to prevent allocation of physical addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory operations are used, then normal read/write functions are maintained, but defects due to short circuits between conducting layers and semiconductor layers cannot be efficiently detected
Solution Approach 1:
The patent applies preliminary action by performing defect detection operations before normal memory operations. Specifically, the method detects short circuits between conducting layers and semiconductor layers by applying detection voltages to selection transistors and measuring currents through memory cells, identifying defective blocks in advance to prevent allocation of physical addresses corresponding to defective regions.
Solution Approach 2:
The patent applies segmentation by dividing the memory device into functional components for detection purposes. The detection method segments the memory cell array into individually detectable units by applying voltages to specific selection transistors (first selection transistor and second selection transistor) and measuring currents through bit lines and source lines, enabling localized defect identification.
2Measurement precision
If detection voltages are applied to selection transistors, then short circuit defects can be detected, but additional operation steps are required
Solution Approach 1:
The patent applies periodic action by implementing detection operations at specific intervals or phases. The method performs detection by applying detection voltages during designated detection periods, alternating between detection operations and normal memory operations, allowing systematic coverage of memory blocks without continuous interruption of normal functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Efficient detection and specification of defect positions, enabling effective management of defective blocks and preventing operational failures in semiconductor memory devices.
Implementation Method 1
a first selection transistor connected between the first wiring and the memory transistor... at a fourth timing between the first timing and the third timing, at least one of a voltage and a current of the first wiring is detected
Data Source
AI summary
A semiconductor memory device includes: a first wiring and a second wiring; a first selection transistor, a memory transistor, and a second selection transistor connected between the first wiring and the second wiring; and a third wiring and a fourth wiring connected to gate electrodes of the first selection transistor and the second selection transistor. From a first timing to a second timing, a first voltage that turns the first selection transistor ON is supplied to the third wiring, and a second voltage that turns the second selection transistor OFF is supplied to the fourth wiring. From the second timing to a third timing, a third voltage that turns the first selection transistor OFF is supplied to the third wiring, and at a fourth timing between the first timing and the third timing, at least one of a voltage and a current of the first wiring is detected.