Memory Defect Management via POST Hash Table
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Solution Overview
Problem
As memory sizes increase, the likelihood of defective memory cells in information handling systems grows, potentially causing system failures and data loss, especially in critical areas like interrupt vector locations and BIOS data areas, necessitating a method to handle memory defects during the Power-On Self Test (POST) phase to ensure system initialization without crashing.
Innovation Solution
A method that utilizes information about known memory defects to optimize system performance by bypassing defective memory locations and updating defect information, allowing the system to operate without crashing, even with partially defective memory components, by selecting an alternate processor or memory address that is error-free for system initialization and calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory size is increased to meet growing information handling needs, then the system's information processing and storage capability is improved, but the likelihood of defective memory cells increases dramatically
Solution Approach 1:
The system performs preliminary actions by identifying and marking defective memory locations during the POST phase before the operating system starts. This early detection allows the system to proactively manage defective cells rather than reacting when errors occur during operation.
Solution Approach 2:
The memory space is segmented into usable and defective regions. The patent creates a data structure (hash table) that divides memory into valid address ranges and defective address ranges, allowing the system to selectively access only healthy memory portions while isolating defective cells.
2Reliability
If traditional error correction schemes are used to avoid crashes on single bit errors, then system stability is improved, but the protection is not quickly available and resident on the memory module itself
Solution Approach 1:
The error protection mechanism is established in advance during the POST phase, before the operating system begins operation. The hash table mapping defective memory locations is pre-computed and stored in non-volatile memory, making the protection immediately available when the system boots without requiring real-time computation during memory access.
Solution Approach 2:
The memory subsystem performs self-diagnosis and self-protection by automatically detecting defective cells during POST and creating its own error correction mapping without external intervention. The system serves its own error protection needs through the hash table mechanism that translates logical memory addresses to physical addresses while bypassing defective regions.
3Reliability
If the system requires certain critical memory areas to be defect-free for proper operation, then system reliability is improved, but the cost of memory components increases
Solution Approach 1:
The patent converts the harmful presence of defective memory cells into a beneficial situation by using the hash table mechanism to redirect accesses away from defective regions. Instead of discarding entire memory modules with defects, the system leverages the defect information to create a mapping that preserves usable memory capacity while isolating problematic cells, thereby reducing waste and cost.
Solution Approach 2:
The system applies different quality requirements to different memory regions. Critical areas such as interrupt vectors and BIOS data structures are protected by ensuring they are allocated from defect-free regions identified during POST, while non-critical memory areas can tolerate the presence of defective cells as long as they are properly mapped around them in the hash table.
4Reliability
If the POST process is made to tolerate memory defects and complete initialization, then system operability is improved, but the complexity of the POST process increases
Solution Approach 1:
The complexity of defect management is extracted from the main POST initialization flow and isolated into a separate hash table construction process. The POST process performs a one-time scan of memory to identify defective cells and builds a hash table mapping, then delegates the actual defect management to this pre-computed data structure rather than continuously checking for defects during every memory operation.
Solution Approach 2:
The hash table acts as an intermediary layer between the CPU and physical memory. Instead of the CPU directly accessing physical memory addresses and encountering defective cells, all memory accesses are mediated through the hash table which translates logical addresses to safe physical addresses, filtering out defective regions before memory access occurs.
Data Source
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AI summary
A method for handling memory defects during the POST phase and memory calibration in single processor and multiprocessor information handling systems is disclosed whereby information regarding the location of a known memory defect is utilized to optimize the performance of an information handling system. Memory defects within system memory are identified and replaced during operation with error free memory space.