Memory Defect Mapping Using Hierarchical CAM Segmentation
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Solution Overview
Problem
Current methods for managing random defects in memory arrays, particularly in MRAM, are inefficient and costly due to the requirement for large content addressable memory (CAM) to map defective addresses to spare locations, leading to impractical solutions with increased memory size and real estate costs.
Innovation Solution
The method involves grouping row and column addresses such that each group has no more than one defective memory cell, allowing for the use of alternate addresses to redirect access to spare locations, thereby reducing the need for extensive spare rows or columns and minimizing the size of the CAM required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large content addressable memory (CAM) is used to map defective addresses to spare locations, then random defects can be managed, but memory size and real estate costs increase significantly
Solution Approach 1:
The memory array is segmented into multiple blocks, each with its own defect management capabilities. By dividing the large memory into smaller segments, the patent reduces the CAM size required for each segment while maintaining overall defect management effectiveness across the entire memory array.
Solution Approach 2:
The patent introduces a hierarchical defect management structure that adds a new dimension to address mapping. Instead of using a single large CAM, the system uses multiple smaller CAMs organized in a hierarchical manner, where each CAM manages a specific block or subset of the memory array, thereby reducing the memory footprint while maintaining comprehensive defect coverage.
2Reliability
If entire rows or columns are replaced with spare rows/columns for defect management, then defective locations can be managed, but the memory array size increases and real estate is wasted
Solution Approach 1:
The patent applies local quality by providing defect management resources (spare rows, spare columns, and CAM entries) only where needed in specific blocks rather than uniformly across the entire memory array. This allows efficient use of spare resources while maintaining reliability in defective regions.
Solution Approach 2:
By segmenting the memory array into blocks with localized defect management, the patent reduces the overall area required for spare rows and columns. Each block can independently manage its defects using smaller spare resources, rather than requiring a global spare structure that would consume significant area.
3Reliability
If two CAMs are employed for maintaining defective row and column addresses, then comprehensive defect coverage is achieved, but the solution becomes costly and impractical
Solution Approach 1:
The patent merges the functionality of multiple CAMs into a unified hierarchical defect management structure. Instead of maintaining separate CAMs for each block, the system uses a hierarchical organization where higher-level CAMs manage cross-block defects and lower-level CAMs handle block-specific defects, reducing overall complexity while maintaining comprehensive coverage.
Solution Approach 2:
The hierarchical CAM structure serves multiple functions: it manages defects within individual blocks, coordinates defect management across blocks, and provides scalable expansion capability. This multi-functional design reduces the need for separate specialized CAM structures for different defect scenarios.
Data Source
AI summary
A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location.