Non-volatile Memory Defect Detection via Pre-sensing and Post-sensing Operations
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Solution Overview
Problem
In three-dimensional integrated semiconductor memory devices, detecting defects in bit lines and word lines is challenging due to the complexity of signals, making it difficult to identify the cause of malfunction and preventing unrecoverable data loss.
Innovation Solution
A non-volatile memory device with a memory cell array, page buffer circuit, control logic circuit, and defect detection circuit that performs pre-sensing and post-sensing operations to disconnect and reconnect bit lines and cell strings, allowing for early detection of defects in bit lines and word lines, thereby preventing data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional sensing operations are used in 3D integrated memory devices, then data processing can proceed, but defects in bit lines and word lines cannot be detected early, leading to unrecoverable data loss
Solution Approach 1:
The patent implements pre-sensing operations before normal data processing to detect defects in bit lines and word lines. The control logic circuit performs preliminary sensing operations that disconnect bit lines from cell strings, allowing defect detection before actual data operations occur. This preliminary action enables early identification of progressive defects, preventing unrecoverable data loss while maintaining normal data processing functionality.
2Productivity
If numerous signals are input from the peripheral circuit for memory operation, then data processing capability is enhanced, but it becomes difficult to detect and interpret the cause of malfunction
Solution Approach 1:
The patent segments the sensing operation into distinct phases: pre-sensing operations for bit line defect detection and post-sensing operations for word line defect detection. The control logic circuit controls disconnection and connection of bit lines to cell strings in specific sequences, separating the detection of different line types. This segmentation simplifies malfunction analysis by systematically isolating potential defect sources while maintaining comprehensive data processing capability through multiple signal inputs.
3Speed
If bit lines and cell strings remain connected during normal operation, then data access is efficient, but progressive defects cannot be detected until data loss occurs
Solution Approach 1:
The patent implements periodic pre-sensing operations that interrupt normal data processing at scheduled intervals. The control logic circuit temporarily disconnects bit lines from cell strings during pre-sensing periods, allowing defect detection without permanently disrupting data access. This periodic action maintains efficient data access speed during normal operations while providing regular opportunities to detect progressive defects before they cause unrecoverable data loss.
Data Source
AI summary
Provided is a non-volatile memory device. The non-volatile memory device includes: a memory cell array including cell strings, each including memory cells respectively connected to word lines; a page buffer circuit including page buffers respectively connected to the memory cells through bit lines, wherein a first page buffer is connected to a first cell string through a first bit line; a control logic circuit configured to control a pre-sensing operation to disconnect the first bit line and the first cell string from each other during a pre-sensing period for detecting a defect of the first bit line and control a post-sensing operation to connect the first bit line and the first cell string to each other in a post-sensing period for detecting defects of the word lines and the first bit line; and a defect detection circuit configured to detect defects of the word lines based the sensing operations.