Semiconductor Memory Defect Detection via Test Region Copying
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Solution Overview
Problem
Semiconductor memory devices face challenges in detecting defects, particularly due to the increasing complexity and miniaturization of their components, which complicates the identification of short failures between active contacts and gate electrodes, leading to difficulties in ensuring reliability and efficiency.
Innovation Solution
The semiconductor memory device incorporates a test region with a dummy pattern and a unique wiring layer configuration that includes test lines and common contacts with protrusion parts, allowing for non-destructive measurement of short failures by applying varying voltages, thereby reducing detection time and costs associated with destructive analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional destructive analysis methods are used for defect detection, then detection capability is achieved, but wafer consumption increases and detection time is extended
Solution Approach 1:
The patent creates a copy of the active contact and gate electrode structure in the test region using dummy patterns. This allows non-destructive testing of the copied structure while inferring defect information about the main active contacts in the memory cell region, thereby eliminating wafer consumption and enabling repeated measurements.
Solution Approach 2:
The test region with dummy patterns is prepared in advance during fabrication, allowing defect detection to be performed before final device completion. This preliminary testing capability enables early identification of defects without consuming finished wafers or requiring destructive analysis of operational devices.
2Reliability
If conventional destructive analysis methods are used for defect detection, then short failures can be identified, but detection time increases
Solution Approach 1:
By creating test copies in the test region, the patent enables rapid electrical measurements without time-consuming destructive analysis. The copied structures can be tested multiple times quickly, significantly reducing detection time while maintaining the ability to identify short failures between contacts and gate electrodes.
Solution Approach 2:
The patent replaces mechanical destructive analysis methods with electrical measurement techniques applied to the test region. This substitution allows for faster, non-destructive detection of short failures by measuring electrical properties such as resistance and capacitance between the dummy contact patterns and gate electrode patterns.
3Area of moving object
If component miniaturization is pursued to reduce device size, then integration density increases, but defect detection difficulty increases
Solution Approach 1:
The patent segments the device into a memory cell region and a separate test region. The test region contains enlarged dummy patterns that replicate the miniaturized active contact and gate electrode structures. This segmentation allows the use of larger, easier-to-measure test structures while maintaining the miniaturized operational device, thereby reducing detection difficulty without compromising device size.
Solution Approach 2:
The dummy patterns in the test region serve as intermediary structures that bridge the gap between miniaturized operational devices and measurement capabilities. These intermediary test structures allow indirect detection of defects in the miniaturized active contacts by providing accessible, larger-scale copies that can be measured with standard equipment.
4Reliability
If complex wiring configurations are added for defect detection, then detection capability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the defect detection functionality into a separate test region that is spatially distinct from the memory cell region. By taking out the testing function and placing it in the test region with dummy patterns, the patent avoids adding complex wiring to the operational memory cells, thereby maintaining device simplicity while enabling comprehensive defect detection capabilities.
Data Source
AI summary
According to various embodiments, a semiconductor memory device includes a substrate that includes a memory cell region and a test region. The semiconductor memory device further includes an active pattern on the memory cell region, a source/drain pattern on the active pattern, a dummy pattern on the test region, a first gate electrode on the dummy pattern, a first common contact, and a first wiring layer. The first wiring layer includes a first test line electrically connected to the first common contact. The first common contact includes a first contact pattern in contact with the dummy pattern, and a first gate contact connected to the first gate electrode. The first gate contact includes a body and a protrusion part. A lowermost level of a top surface of the active pattern is lower than a lowermost level of a top surface of the dummy pattern.