Memory Device Defective Chip Repair via ECC Data Transfer
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Solution Overview
Problem
As memory devices integrate more data, they face challenges in handling defective memory cells without interrupting system operations, leading to potential data loss and performance degradation.
Innovation Solution
A memory device configuration that includes multiple memory chips, an ECC memory chip for error correction, and a controller to mark defective memory cells, allowing for post-package repair by transferring data to redundancy lines, enabling continuous operation without system interruption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If post package repair is executed on defective memory cells, then reliability is improved, but system operation interruption occurs
Solution Approach 1:
The memory device is divided into multiple memory chips, and the repair process is segmented by handling defective cells in specific chips while others continue operating normally. This allows the system to maintain functionality during repair operations on individual chips.
Solution Approach 2:
Data from defective memory chips is pre-transferred to ECC memory chips before the repair process begins. This preliminary data migration ensures that no data loss occurs during the repair operation and allows the system to continue operating without interruption.
2Loss of information
If data transfer to ECC memory chip is performed, then data safety is improved, but device complexity increases
Solution Approach 1:
The ECC memory chip serves multiple functions: it provides error correction for data from normal memory chips and also serves as a temporary storage destination for data being transferred from defective memory chips during repair operations. This multi-functionality reduces the need for additional dedicated components.
Solution Approach 2:
The ECC memory chip acts as an intermediary between the defective memory chips and the main memory system. It temporarily holds data during the transfer process and provides error correction, simplifying the overall data management architecture during repair operations.
3Quantity of substance
If multiple memory chips are used, then storage capacity is improved, but difficulty of detecting defective cells increases
Solution Approach 1:
The controller continuously monitors the operational status of each memory chip and provides feedback to identify defective cells. By tracking read/write errors and operational anomalies across multiple chips, the system can reliably detect and isolate defective cells without difficulty.
Data Source
AI summary
A memory device includes a plurality of memory chips storing and outputting data in response to a control command and an address command, at least one ECC memory chip providing an error check and correction (ECC) function on the data stored and output by the plurality of the memory chips, and a controller, marking a memory chip in which a defective memory cell is detected among the plurality of memory chips, as a defective memory chip, storing data of the defective memory chip in the ECC memory chip, and controlling the defective memory chip to execute a post package repair (PPR).