Memory Device Delay Circuit for PDA Mode Signal Synchronization
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Solution Overview
Problem
Current memory devices require additional circuits to synchronize signals in PDA mode, leading to increased area and complexity, as they struggle to determine the validity of mode register set commands based on the signal level of the 0th data pad, resulting in inefficient use of space.
Innovation Solution
Incorporating a decoder circuit to activate setting and write signals, a delay circuit to generate delayed write signals, and a path selection circuit to route these signals appropriately, allowing for a setting operation in response to the delayed write signal and input signals, thereby controlling latency and minimizing area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional circuits are added to synchronize signals in PDA mode, then the ability to determine validity of mode register set commands is improved, but the area of the memory device increases
Solution Approach 1:
The delay circuit is designed to serve dual purposes: it delays write signals during normal write operations and delays setting signals during PDA mode operations. By making the delay circuit multi-functional, the patent eliminates the need for separate synchronization circuits, thereby maintaining command validity determination capability in PDA mode without increasing device area.
Solution Approach 2:
The patent merges the PDA mode signal synchronization function into the existing delay circuit that is already present for write operations. This consolidation combines multiple signal processing functions into a single circuit, avoiding the need for additional dedicated PDA mode circuits and thus preventing area increase.
2Adaptability or versatility
If multiple circuits are provided for synchronizing timings of signals, then the PDA mode operation is supported, but the complexity of the device increases
Solution Approach 1:
The delay circuit is designed to serve dual purposes: it delays write signals during normal write operations and delays setting signals during PDA mode operations. By making the delay circuit multi-functional, the patent eliminates the need for separate synchronization circuits, thereby maintaining command validity determination capability in PDA mode without increasing device area.
Solution Approach 2:
The patent merges the PDA mode signal synchronization function into the existing delay circuit that is already present for write operations. This consolidation combines multiple signal processing functions into a single circuit, avoiding the need for additional dedicated PDA mode circuits and thus preventing area increase.
3Loss of time
If a delay circuit is used to delay write signals, then the write latency is controlled, but the setting operation timing must be synchronized
Solution Approach 1:
The delay circuit is designed to serve dual purposes: it delays write signals during normal write operations and delays setting signals during PDA mode operations. By making the delay circuit multi-functional, the patent eliminates the need for separate synchronization circuits, thereby maintaining command validity determination capability in PDA mode without increasing device area.
Data Source
AI summary
A memory device includes a decoder circuit configured to activate a setting signal and a write signal if a setting command is applied when a reference mode is set; a delay circuit configured to delay and to generate a delayed write signal; and a setting circuit configured to perform a setting operation in response to the delayed write signal and an input signal of a predetermined pad at the time of setting of the reference mode and to perform the setting operation in response to the setting signal when the reference mode is not set.