Memory Delay Circuit Sharing Single Unit for Read Write Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional latency control circuits in memory devices require multiple D-flipflops for delaying signals, leading to increased circuit area and current consumption due to the need for separate delay units for different signals.
Innovation Solution
A delay circuit that shares a single delay unit to delay multiple signals by generating a distinguishment signal to differentiate between the signals, allowing the same delay unit to handle both read and write commands, thereby reducing the number of required delay units and minimizing circuit area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate delay units are used for different signals (read command, write command, address), then each signal can be delayed independently, but the circuit area and current consumption increase
Solution Approach 1:
A single delay unit is designed to handle multiple signal types (read command, write command, address) by using a signal type identification mechanism. The delay unit dynamically adjusts its operation based on the input signal type, allowing one unit to perform functions that previously required multiple separate units, thereby reducing circuit area while maintaining delay accuracy for each signal type
Solution Approach 2:
Multiple separate delay units for different signals are merged into a single shared delay unit. The merging is achieved by adding a signal type detection mechanism that routes different signals to the same delay unit with appropriate delay parameters, combining the functionality of multiple units into one while preserving the independent delay control needed for each signal type
2Reliability
If multiple D-flipflops are used for delaying different signals, then each signal can be delayed independently, but the current consumption increases
Solution Approach 1:
The delay unit is designed with multi-functionality to handle different signal types using the same hardware resources. By identifying the signal type and applying the appropriate delay configuration, the same D-flipflops are reused for different signals at different times, reducing the total number of D-flipflops needed and thereby reducing current consumption while maintaining precise latency control for each signal type
Solution Approach 2:
The delay unit discards the previous signal type configuration and recovers/reconfigures for the new signal type. This allows the same hardware resources (D-flipflops) to be reused for different signals sequentially, rather than being permanently allocated to each signal type, reducing overall current consumption while maintaining the ability to provide precise delay control for each signal type when needed
Data Source
AI summary
A delay circuit includes a delay unit configured to generate a delayed transfer signal by delaying a transfer signal corresponding to a first signal or a second signal, a distinguishment signal generation unit configured to generate a distinguishment signal which represents to what signal the transfer signal correspond between the first signal and the second signal and a delayed signal generation unit configured to output the delayed transfer signal as a first delayed signal or a second delayed signal in response to the distinguishment signal.