Memory Thermal Management via Autonomous Delay Intervals

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Solution Overview

Problem

Integrated circuit devices, such as memory devices, generate heat during operation, exceeding their ability to dissipate it, leading to increased temperatures that can throttle operations unless actively managed by external processors, which is not always feasible.

Innovation Solution

The memory device autonomously adjusts its operation pace by inserting a delay interval in array operations based on temperature indications, allowing for thermal management without external control, using a temperature sensor to determine the duration of the delay interval, which increases with higher temperatures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the memory device operates continuously at high speed, then productivity is improved, but temperature increases causing thermal throttling

Engineering Contradiction:
Improveoperation paceVSAvoiddevice temperature
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The memory device implements periodic thermal management by inserting delay intervals between array operations when temperature exceeds thresholds. This creates a periodic on-off pattern where operations proceed normally below thresholds and are paused above thresholds, allowing the device to rhythmically dissipate heat while maintaining high productivity during cool periods

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The memory device dynamically adjusts its operation pace based on real-time temperature conditions. By making the operation rate variable rather than fixed, the device can accelerate during cool periods and decelerate during hot periods, optimizing the balance between productivity and thermal management

Inventive Principle:
Principle #15Dynamics

2Temperature

If external processors actively manage thermal throttling, then temperature control is improved, but device complexity increases

Engineering Contradiction:
Improvetemperature controlVSAvoidcontrol system complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The memory device performs thermal management autonomously using internal temperature sensors and control logic. The device monitors its own temperature, compares it against thresholds, and automatically adjusts operation pace without requiring external processors, thereby simplifying the overall system while maintaining effective temperature control

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The memory device implements a closed-loop feedback system where temperature sensors continuously monitor device temperature and feed this information back to control logic. The control logic then adjusts operation pace based on this feedback, creating a self-regulating thermal management system that maintains temperature within safe limits

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively mitigates heat generation by reducing operational pace within the memory device in response to temperature, ensuring it operates within safe thermal limits without requiring active external control, thus preventing throttling and maintaining performance.

Implementation Method 1

a temperature sensor to determine the duration of the delay interval, which increases with higher temperatures

Methodology Applied
Scientific EffectTemperature sensing: Thermistor

Data Source

PatentUS11915764B2Apparatus and methods for thermal management in a memory
Publication Date: 2024.02.27 MICRON TECHNOLOGY INC
  • US11915764B2 patent drawing
  • US11915764B2 patent drawing
  • US11915764B2 patent drawing

AI summary

Memories might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the memory to initiate an array operation on the array of memory cells, indicate an unavailability to initiate a next array operation, append a delay interval to an array access time of the array operation, and indicate an availability to initiate a next array operation in response to a completion of the delay interval. The delay interval might have a duration determined in response to an indication of temperature.