Memory Delay Signaling for Row Hammer Refresh Protection
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Solution Overview
Problem
Memory devices are vulnerable to 'waterfall' attacks that exploit row hammer effects, causing data degradation by overwhelming memory arrays with targeted row hammer activity, which existing refresh mechanisms fail to prevent effectively.
Innovation Solution
Memory devices are equipped with a refresh management circuit that detects such attacks by monitoring activation commands and asserts a signal to the controller, requesting a delay during which internal refresh operations are performed to mitigate row hammer effects, thereby preventing further commands from being sent.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing refresh mechanisms are used to maintain memory cells, then memory operations can continue normally, but the memory device is vulnerable to waterfall attacks causing data degradation
Solution Approach 1:
The patent applies preliminary anti-action by detecting row hammer activity patterns before they cause data degradation and proactively asserting a delay signal to prevent further harmful activations. The refresh management circuit monitors activation commands and identifies waterfall attack patterns, then preemptively blocks additional commands before they can accumulate enough to flip bits in victim rows.
Solution Approach 2:
The patent implements preliminary action by performing targeted refresh operations on potentially affected rows during the delay period. Instead of waiting for bit flips to occur and then correcting them, the system proactively refreshes rows that are at risk based on detected attack patterns, preventing data degradation before it happens.
2Reliability
If the memory device performs targeted refresh operations during attacks, then data integrity is maintained, but command processing is delayed
Solution Approach 1:
The patent applies partial action by selectively refreshing only the rows that are targeted by the waterfall attack rather than performing a full memory refresh. The refresh management circuit identifies specific victim rows based on activation patterns and directs refresh operations only to those rows, minimizing the delay while maintaining data integrity for the affected memory regions.
Solution Approach 2:
The patent segments the refresh operation to handle only the affected portion of memory during an attack. Instead of refreshing the entire memory array, the system divides the memory into affected and unaffected regions and applies refresh operations only to the affected segments, reducing the overall time penalty while protecting critical data.
3Difficulty of detecting and measuring
If the memory device monitors activation commands to detect attacks, then attack detection capability is improved, but device complexity increases
Solution Approach 1:
The patent implements feedback by continuously monitoring activation commands and using the detected patterns to control refresh operations. The refresh management circuit counts activations on adjacent rows and uses this feedback information to determine when to assert the delay signal and which rows require refreshing, creating a closed-loop system that adapts to detected attack patterns.
Solution Approach 2:
The memory device performs self-diagnosis and self-protection by autonomously detecting waterfall attacks and initiating appropriate countermeasures without external intervention. The refresh management circuit independently monitors activation patterns, identifies attack conditions, asserts delay signals to the controller, and triggers targeted refresh operations, enabling the device to protect itself against attacks.
Data Source
AI summary
Memory devices, systems including memory devices, and methods of operating memory devices are described in which waterfall attacks can be prevented from degrading data by alerting a memory controller that the memory device requests time to perform internal management operations, and should not be sent any further commands (e.g., activate commands) for a predetermined amount of time. In one embodiment, a memory device includes an external pin, a mode register, a memory array including a plurality of rows of memory cells, and circuitry configured to: determine that a criterion to perform an internal management operation on a subset of the plurality of rows has been met, transmit, in response to determining the criterion has been met, a signal to the external pin, determine a duration corresponding to the internal management operation, and write a bit value indicative of the determined duration to the mode register.