Memory Descrambler Using Sub-Syndrome Weights for Fast Sequence Detection

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Solution Overview

Problem

Current memory systems face challenges in quickly identifying the correct scrambler sequence among multiple scrambler sequences, leading to prolonged latency in data descrambling processes.

Innovation Solution

A descrambler that calculates sub-syndrome weights using a set parity check matrix to quickly identify the correct scrambler sequence among multiple scrambler sequences, facilitating efficient data descrambling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple scrambler sequences are used for data scrambling, then data security and reliability are improved, but the time required to identify the correct scrambler sequence increases

Engineering Contradiction:
Improvedata securityVSAvoidsequence identification time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the parity check matrix into multiple sub-parity check matrices, each corresponding to a different scrambler sequence. This allows the descrambler to independently verify each sequence using dedicated sub-matrices, significantly reducing the time required to identify the correct sequence while maintaining security through multiple sequences

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent pre-calculates and stores multiple sub-parity check matrices before actual data processing. When descrambling is needed, the system can immediately use these pre-prepared matrices to verify different scrambler sequences without performing full matrix calculations, thus reducing identification time while maintaining reliability

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If multiple sub-syndrome weights are calculated for each descrambled sequence, then the precision of correct sequence identification is improved, but the computational complexity increases

Engineering Contradiction:
Improvesequence identification precisionVSAvoidcomputational complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies different sub-parity check matrices to different portions or aspects of the descrambled sequences, calculating sub-syndrome weights locally for each sequence using its corresponding sub-matrix. This localized approach improves identification precision by focusing computational resources on relevant portions of the data while managing overall complexity through the segmented structure

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11502703B2Descrambler for memory systems and method thereof
Publication Date: 2022.11.15 SK HYNIX INC
  • US11502703B2 patent drawing
  • US11502703B2 patent drawing
  • US11502703B2 patent drawing

AI summary

A descrambler receives data from a memory device. The descrambler calculates a sub-syndrome weight for multiple bits in each of the plurality of descrambled sequences using a set parity check matrix to generate multiple sub-syndrome weights, one for each of the plurality of descrambled sequences. The descrambler selects a sub-syndrome weight among the multiple sub-syndrome weights. The descrambler determines, as a correct scrambler sequence for descrambling the data, a scrambler sequence corresponding to the selected sub-syndrome weight, among the plurality of scrambler sequences.