Memory Detection Circuit Identifying Failed Bits
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Solution Overview
Problem
As semiconductor memory devices increase in density, memory cells exhibit reduced physical volume, stored charges, and noise tolerance, leading to increased electromagnetic interference and data loss, with design or manufacturing defects potentially causing failed addresses, affecting yield and reliability.
Innovation Solution
A detection circuit comprising a mode register data processing module, external data transmission module, and comparison module is used to write preset data into a memory array, read target data, and compare for abnormal transmission, storing results in a mode register to identify failed bits and improve efficiency and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased to meet storage capacity demand, then storage capacity is improved, but noise tolerance and data reliability deteriorate due to reduced physical volume and increased electromagnetic interaction
Solution Approach 1:
The patent applies preliminary action by performing data transmission testing before the memory device is officially released. Test data is written into the memory array in advance, and detection circuits compare expected data with actual read data to identify failed bits beforehand. This allows defective memory cells to be detected and marked prior to product shipment, ensuring that only reliable data regions are used in final products.
Solution Approach 2:
The memory device performs self-diagnosis through built-in detection circuits that automatically write test data, read back data, and compare results to identify failed bits. The system uses its own internal resources (data transmission modules, comparison modules, and mode registers) to conduct reliability testing without requiring external test equipment, enabling self-verification of data integrity.
2Reliability
If detection circuits are added to identify failed bits, then data reliability is improved, but device complexity increases
Solution Approach 1:
The detection circuit utilizes existing multi-functional components within the memory device. The data transmission module serves both normal data operations and test data writing. The comparison module reuses existing data comparison capabilities. The mode register, which normally stores operational parameters, is also used to store detection results and failed bit information. This multi-functional approach allows reliability testing without adding dedicated separate test components.
Solution Approach 2:
The patent introduces a mode register as an intermediary component that bridges the detection circuit and the memory array. The mode register stores both normal operational mode information and test detection results, acting as a mediator that allows the detection system to communicate with the memory array without requiring complex direct test interfaces. This intermediary structure simplifies the overall test architecture.
Data Source
AI summary
A mode register data processing module is configured to write, in response to a mode register write enable command, first preset data into a reserved mode register in a mode register; an external data transmission module is configured to write, in response to an enable signal, initial data into a memory array via an internal data transmission module according to the first preset data and a preset encoding rule, and is further configured to read target data from the memory array in response to a read command; and a comparison module is configured to determine whether there is an abnormal data transmission based on a comparison result of the first preset data and the target data, and store the comparison result to a preset position in the mode register.