Memory Detection Circuit for Simultaneous Word Line Activation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Electronic memory arrays are vulnerable to attacks through simultaneous activation of multiple word lines, which can lead to data manipulation and security breaches, as existing protection mechanisms are inadequate in detecting such invasive attacks.
Innovation Solution
A memory arrangement with separate columns for storing useful data and verification data, where precomputed bit patterns are stored in additional columns, and a detection circuit monitors bit lines for logic combinations during read access to detect simultaneous activation of multiple word lines, triggering an alarm if the Hamming weight of the resultant pattern exceeds the precomputed weight, indicating an attack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verification data columns are added to the memory array to detect simultaneous word line activation, then security against attacks is improved, but memory array complexity increases
Solution Approach 1:
The memory array is segmented into two distinct column types: first column types for storing useful data and second column types for storing verification data. This segmentation allows the verification data to be independently managed and processed, enabling detection of simultaneous word line activation attacks without interfering with normal data storage operations.
Solution Approach 2:
The verification data columns act as an intermediary mechanism between the memory storage function and the security detection function. By storing precomputed verification patterns in separate columns, the system can detect attacks through comparison operations without compromising the primary data storage capability.
2Measurement precision
If precomputed bit patterns are stored in additional memory columns for attack detection, then detection precision is improved, but memory resource consumption increases
Solution Approach 1:
Verification data in the form of precomputed bit patterns are stored in the second column types during manufacturing or initialization. These precomputed patterns enable rapid detection of simultaneous word line activation attacks during normal operation without requiring complex real-time computation, thus improving detection precision while using memory resources efficiently.
3Difficulty of detecting and measuring
If the memory array is extended with additional columns for verification data, then area of memory array increases, but detection capability is improved
Solution Approach 1:
The extended memory array structure serves multiple functions: the first column types store useful data for normal operations, while the second column types store verification data for security detection. This multi-functionality allows the same memory array structure to simultaneously support data storage and attack detection, improving detection capability while minimizing the additional area required.
Data Source
AI summary
A memory arrangement having a memory cell array, wherein each column is associated with a bit line and each row is associated with a word line, wherein the columns have first columns of memory cells that store useful data, and columns of memory cells of a second column type that store prescribed verification data, wherein during a read access operation the memory cells of at least the columns of memory cells of the second column type set the associated bit line to a value that corresponds to a logic combination of the values stored by the memory cells of the column of the second column type that belong to rows of memory cells addressed during the read access operation, and a detection circuit that is configured to, during a read access operation, detect whether a bit line associated with a column of memory cells of the second column type is set to a value that corresponds to the logic combination of values stored by memory cells of the column of the second column type of memory cells and whose values belong to different rows of memory cells.