In-Memory Computing Digital Detector for Accurate Bit-Line Current Sampling
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Solution Overview
Problem
Existing in-memory computation devices suffer from low computational accuracy due to errors in current measurement caused by the non-linear behavior of analog-to-digital converters (ADCs), especially at high currents.
Innovation Solution
The implementation of an improved digital detector in an in-memory computation device, which samples the bit line current and generates control signals to adjust the selection current, thereby reducing the additional charge acquired during the delay interval and ensuring more uniform charge packets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If an ADC is used to measure the current generated by in-memory computation device, then the current can be discretized into charge packets, but the measurement accuracy deteriorates due to non-linear behavior and additional charge acquisition during delay interval
Solution Approach 1:
The patent applies preliminary action by pre-calculating compensation values for the delay interval charge (Qadd) based on expected current ranges. The system determines the appropriate charge packet size in advance considering the delay interval effects, and adjusts the switching threshold voltage (Vth,sw) beforehand to compensate for expected additional charge acquisition. This allows the system to maintain uniform charge packets despite the inherent ADC delay interval.
Solution Approach 2:
The patent changes the switching threshold voltage parameter (Vth,sw) dynamically based on the current measurement range. By adjusting Vth,sw as a compensating parameter, the system offsets the additional charge acquired during the delay interval. The patent also modifies the charge packet size parameter to ensure uniformity across different current values, directly addressing the non-linear behavior of the ADC.
2Measurement precision
If the switching threshold voltage is set to achieve ideal uniform charge packets, then measurement accuracy should be improved, but the delay interval causes additional charge acquisition that varies with current value
Solution Approach 1:
The patent applies preliminary anti-action by introducing a compensating voltage (Vth,sw) that acts in opposition to the harmful additional charge acquisition during the delay interval. This compensating voltage is determined in advance based on the expected current value and is applied before the measurement occurs, thereby preemptively counteracting the non-linear effect and ensuring uniform charge packets across different current ranges.
3Adaptability or versatility
If the ADC measures high currents, then the measurement range is extended, but the non-linear behavior and additional charge acquisition increase, worsening measurement accuracy
Solution Approach 1:
The patent applies dynamics by making the charge packet size and switching threshold voltage adaptive rather than fixed. The system dynamically adjusts these parameters based on the current measurement range, allowing optimal performance across both low and high current values. This dynamic adaptation ensures that the charge packets remain uniform and the measurement accuracy is maintained even when measuring high currents that would otherwise cause significant additional charge acquisition.
Data Source
AI summary
An in-memory computation device receives an input signal and provides an output signal. The device includes a memory array with memory cells coupled to word lines that receive word line activation signals indicative of the input signal and coupled to bit lines that generate bit line currents; and a digital detector for sampling the bit line current and, in response, providing the output signal. A digital detector includes: a control stage that compares the bit line current with at least one reference current and generates corresponding control signals; a selection stage that generates a total selection current based on the first bit line current and on the control signals; an integration stage that samples the total selection current; and a charge counter stage that generates the output signal on the basis of a sampled first total selection current and the control signals.