Memory Device Test Mode Adaptive Bias Control
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Solution Overview
Problem
Current memory devices face challenges in achieving uniform operation speeds across different memory dies and word line groups, leading to inefficiencies in programming and testing processes.
Innovation Solution
A method is introduced to set program biases and offsets based on the operation speed of each memory die and word line group, allowing for the detection of defects using varying voltages, thereby equalizing program operation speeds and improving test performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If uniform operation speeds are targeted across all memory dies, then manufacturing consistency is improved, but test time and complexity increase due to the need for individualized bias settings
Solution Approach 1:
The patent applies parameter changes by adjusting program bias values based on measured operation speeds. Each memory die receives a customized program bias that compensates for its specific speed characteristics, transforming a uniform test approach into an adaptive parameter-based solution that maintains consistency without requiring complex test procedures
Solution Approach 2:
The patent implements preliminary action by measuring the operation speed of each memory die before conducting the main test. This preliminary measurement allows the system to pre-determine appropriate program biases and offsets, eliminating the need for complex real-time adjustments during testing and reducing overall test complexity
2Productivity
If individualized program biases are set for each memory die, then programming speed consistency is improved, but setup time and process complexity increase
Solution Approach 1:
The patent applies self-service by enabling memory dies to effectively calibrate themselves through the measurement and bias setting process. Each die's operation speed is measured and used to determine its own optimal program bias, eliminating the need for manual intervention or complex external configuration systems
Solution Approach 2:
The patent implements feedback by using the measured operation speed of each memory die to adjust its program bias. This closed-loop approach ensures that programming speed consistency is achieved through continuous measurement and adjustment, rather than through time-consuming preliminary setup procedures
3Measurement precision
If multiple offsets are set for different word line groups, then defect detection accuracy is improved, but test complexity and measurement requirements increase
Solution Approach 1:
The patent applies local quality by setting different offsets for different word line groups based on their specific operation characteristics. This localized approach allows each word line group to be tested with parameters optimized for its particular characteristics, improving defect detection accuracy without requiring a completely complex test configuration across the entire device
4Reliability
If high voltages are varied based on program bias and offsets, then defect detection capability is improved, but power consumption and energy requirements increase
Solution Approach 1:
The patent applies parameter changes by varying high voltages based on the program bias and offset settings for each memory die and word line group. This adaptive voltage approach ensures that sufficient power is applied only where needed for effective defect detection, rather than uniformly across all components, thereby improving detection capability while managing power consumption
Data Source
AI summary
The present technology relates to an electronic device. A method of operating a memory device having improved test performance according to the present technology includes setting a plurality of program biases corresponding to a plurality of memory dies, respectively, based on an operation speed of each of the plurality of memory dies, setting a plurality of offsets corresponding to a plurality of word line groups, respectively, based on an operation speed of each of the plurality of word line groups included in a selected block of a selected memory die among the plurality of memory dies, and detecting a defect of a target block of the selected memory die using a plurality of high voltages and a set low voltage determined based on a program bias corresponding to the selected memory die and the plurality of offsets.