Memory Device Adaptive Erase Voltage Control
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Solution Overview
Problem
Nonvolatile memory devices, such as flash memory, face challenges in achieving optimal threshold voltage distribution during erase operations, leading to inefficiencies in data retention and storage due to slow write and read speeds.
Innovation Solution
A memory device with a memory cell array and peripheral circuit that performs erase voltage application, first and second erase verify operations, and soft programming, where the control logic sets the start erase voltage based on the results of these operations to optimize the erase process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a fixed erase voltage is applied during erase operations, then the erase process is simple and fast, but the threshold voltage distribution of memory cells deteriorates
Solution Approach 1:
The patent applies dynamics by making the erase voltage adjustable rather than fixed. The control logic dynamically changes the erase voltage based on verification results, transitioning from a static voltage application to a dynamic adaptive process that optimizes threshold voltage distribution while managing operational complexity
Solution Approach 2:
The patent implements feedback through verify operations that monitor the erase process. The control logic uses verification results to determine whether to adjust the erase voltage, creating a closed-loop system where output information feeds back to modify the input parameters for improved threshold voltage distribution
2Manufacturing precision
If the erase voltage is increased to improve threshold voltage distribution, then the erase effectiveness improves, but the risk of damaging memory cells increases
Solution Approach 1:
The patent uses dynamics to adjust the erase voltage adaptively rather than applying a constantly high voltage. The control logic modulates the voltage level based on real-time verification feedback, allowing high voltage to be applied only when necessary to improve threshold voltage distribution while avoiding unnecessary damage risk
Solution Approach 2:
The patent applies parameter changes by modifying the erase voltage parameter based on verification results. The control logic changes the voltage parameter dynamically, increasing it only when verification indicates poor threshold voltage distribution, thereby improving effectiveness while minimizing the risk of cell damage from excessive voltage
3Manufacturing precision
If multiple verify operations are performed to ensure proper erasing, then the threshold voltage distribution improves, but the operation time increases
Solution Approach 1:
The patent implements feedback through verify operations that provide information about the erase status. This feedback mechanism allows the system to make informed decisions about whether additional verify operations are necessary, optimizing the balance between achieving proper threshold voltage distribution and minimizing operation time
Solution Approach 2:
The patent applies partial action by performing verify operations selectively rather than always executing the full sequence. The control logic determines whether one or two verify operations are sufficient based on erase conditions, avoiding unnecessary operations that would increase time loss while ensuring adequate verification for proper threshold voltage distribution
Data Source
AI summary
A memory device and an operating method of the memory device is disclosed. The memory device includes a memory cell array including a plurality of memory blocks. The memory device further includes a peripheral circuit for performing an erase voltage application operation, a first erase verify operation, and a second erase verify operation on a selected memory block among the plurality of memory blocks. The memory device also includes a control logic for setting a start erase voltage of an erase operation, based on a result of the first erase verify operation, and controlling the peripheral circuit to perform the second erase verify operation when it is determined that the first erase verify operation on the selected memory block has been passed.