Memory Device Address Decoding for Non-Power-of-Two Dimensions
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Solution Overview
Problem
Current memory technologies face challenges in fitting high-capacity memory circuits into small packages due to the rigid form of memory planes, which are often organized into matrices with dimensions that are powers of two, limiting flexibility and leading to cost overruns and production issues, especially for page-programmable memories like EEPROMs.
Innovation Solution
The memory device employs a physical memory plane with a non-power-of-two number of lines and columns, using Euclidean division for address decoding, allowing for adaptive formatting to fit within smaller packages by addressing only parts of the memory plane based on logical addresses and the remainder of Euclidean division, enabling efficient use of space and reducing the need for standard metal plates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the memory plane is organized into matrices with dimensions that are powers of two, then the routing of peripheral circuits can be easily adapted to the package form, but the memory circuit occupies more area and cannot fit into smaller packages
Solution Approach 1:
The memory plane is segmented into multiple blocks, where each block can be independently addressed. This allows the memory to be organized in a non-power-of-two configuration (e.g., 256x1024 instead of 512x512) while maintaining efficient routing. The segmentation enables flexible adaptation to different package sizes without requiring the entire memory matrix to follow power-of-two dimensions.
Solution Approach 2:
The patent changes the dimensional parameters of the memory matrix from traditional power-of-two values to non-power-of-two values (such as 256 columns and 1024 rows). This parameter change allows optimization of the memory layout to fit smaller packages while maintaining the same storage capacity, thereby reducing the overall circuit area occupied.
2Quantity of substance
If the memory circuit area is increased to fit higher capacity memories, then the memory capacity increases, but the flexibility to adapt to standard package forms decreases
Solution Approach 1:
Instead of increasing memory capacity by expanding the matrix in a square configuration (which increases area), the patent transitions to a rectangular configuration with different row and column dimensions (e.g., 256x1024). This dimensional change allows the same capacity to be achieved with a different area footprint, improving adaptability to standard package forms while maintaining high capacity.
3Area of stationary object
If non-power-of-two memory dimensions are used, then the package size can be reduced, but the address decoding complexity increases
Solution Approach 1:
The address decoding logic is designed in advance to handle non-power-of-two dimensions. The row and column decoders are pre-configured with the specific dimensions (e.g., 10 bits for rows, 8 bits for columns), allowing the system to efficiently decode addresses without requiring complex runtime calculations. This preliminary design approach maintains simplicity despite the non-standard dimensions.
Data Source
AI summary
The memory device comprises a physical memory plane (PMP) comprising m first physical lines (RGP1i) extending along a first direction and n second physical lines (RGP2j) extending along a second direction, reception means for receiving a logical address (ADR) designating a first logical line (RG1i) and a second logical line (RG2j) of a matrix logical memory plane (PML), possessing 2p first logical lines extending along the first direction and 2q second logical lines extending along the second direction, in that m and n are each different from a power of two, m being a multiple of 2k, k being less than or equal to p, and the product of m and n being equal to the nearest integer above 2p+q, and in that it comprises means for addressing the physical memory plane (PMP) that are configured to address a first physical line and a part only of a second physical line on the basis of the content of the said logical address received and of the remainder of a Euclidean division of a part of the content of this logical address received by m/2k.