Memory Device Internal Address Generation for Intermittent Failure Testing
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Solution Overview
Problem
Existing memory device test methods are inefficient and unreliable in detecting intermittent failures due to the need for repeated command and address inputs, which wastes time and is affected by variations in internal clock cycles caused by PVT conditions, making it difficult to maintain consistent stress application during testing.
Innovation Solution
A semiconductor system and method that automatically generates and counts a toggling row active signal to output addresses internally, reducing unnecessary command and address input times and maintaining consistent stress application by deactivating the test enable signal when a target activation number is reached, even if the internal clock cycle varies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If repeated command and address inputs are used to screen intermittent failures, then failure detection capability is improved, but test time increases significantly
Solution Approach 1:
The memory device performs self-testing by automatically generating row active signals and counting their toggling without requiring external command and address inputs for each stress application. The internal address generation block and counter circuit enable the device to autonomously apply stress and detect intermittent failures, eliminating the time-consuming repeated command input process while maintaining failure detection capability
Solution Approach 2:
The test enable signal is activated in advance to initiate the internal stress application process. The address generation block pre-generates address signals and the counter circuit is prepared to count row active signal toggling before the actual stress test begins, allowing the system to quickly enter the failure detection phase without repeated command inputs
2Stability of the object's composition
If external commands and addresses are repeatedly input to maintain consistent stress application, then stress consistency is improved, but internal clock cycle variations affect test reliability
Solution Approach 1:
The memory device uses its internal address generation block to automatically generate row active signals based on predetermined addresses during test mode. The internal counter circuit counts the toggling of these self-generated signals without requiring external synchronization, eliminating the impact of PVT variations on stress application consistency. The system serves itself by generating all necessary test signals internally
Solution Approach 2:
The counter circuit continuously monitors the toggling number of row active signals and provides feedback to determine when the stress test should terminate. When the counter reaches the target activation number, it generates a termination signal that deactivates the test enable signal, ensuring that the stress application consistency is maintained and the test evaluates reliability accurately without being affected by external clock variations
3Ease of operation
If manual address changes are performed during testing, then stress application control is improved, but device complexity and operation difficulty increase
Solution Approach 1:
The address generation block automatically generates and increments address signals during the stress test without requiring external intervention. The system self-manages the address sequence and row active signal generation, simplifying operation while the internal counter and termination logic maintain precise control over stress application. This self-service mechanism reduces both operational complexity and device complexity
Solution Approach 2:
The address generation block serves multiple functions: it generates addresses for normal memory operations, generates row active signals for stress testing, and provides addresses to the counter circuit for toggling detection. This multi-functionality eliminates the need for separate test control circuits, reducing device complexity while maintaining ease of operation through unified address management
Data Source
AI summary
A semiconductor system includes: a first semiconductor device suitable for outputting a command; and a second semiconductor device suitable for activating a test enable signal based on the command, generating a counting signal representing a toggling number of a row active signal for an activation period of the test enable signal, increasing and outputting an address when the counting signal reaches a target activation number, and deactivating the test enable signal when the counting signal reaches the target activation number and the address has a maximum value.