Semiconductor Memory Device Dynamic Address Mapping for Failed Bit Isolation
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Solution Overview
Problem
Nonvolatile semiconductor memory devices, such as ReRAM, face read errors and performance degradation due to manufacturing defects and long-term reliability issues, leading to decreased yield and increased complexity in error correction.
Innovation Solution
A semiconductor memory device with a sequence control circuit that reads flag information to determine the number of failed bits, switching between first and second address mappings to isolate failed data, thereby reducing the load on error correction circuits and improving data readability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional address mapping is used in nonvolatile semiconductor memory devices, then the device structure remains simple, but read errors occur and yield decreases due to manufacturing defects and reliability issues
Solution Approach 1:
The patent implements dynamic address mapping that switches between first and second address mappings based on flag information. The sequence control circuit selects the appropriate mapping mode dynamically, allowing the system to adapt to different data states and isolate failed bits effectively, thereby improving reliability without permanent complexity
Solution Approach 2:
The patent uses preliminary flag information to indicate the state of memory cells before actual data reading. By checking flag information first, the system can determine whether to use first or second address mapping in advance, preventing read errors before they occur and enabling proactive error management
2Reliability
If error correction circuits are added to handle manufacturing defects, then data readability improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent introduces flag information as an intermediary element that mediates between the memory cell array and the read operation. The flag information carries state information about failed bits, allowing the sequence control circuit to adjust address mapping without requiring complex error correction circuits. This intermediary approach provides error management functionality with minimal additional complexity
Solution Approach 2:
The patent segments the address mapping into two distinct modes (first and second address mappings) that can be selected based on flag information. This segmentation allows the system to handle different data states separately, isolating failed bits through appropriate mapping selection rather than using complex error correction circuits
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a memory cell array including a plurality of memory cells, a first register configured to store data of the memory cells, and a sequence control circuit configured to control the memory cell array and the first register. In at least a data read operation of the memory cells, the sequence control circuit reads out, from the memory cell array, data including flag information representing whether the number of failed bits is in an allowable range.