Memory Device Address Translation for Page Size Mismatch
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Solution Overview
Problem
Existing memory management techniques, such as multi-level paging, face performance issues due to the overhead of page table walks, which involve multiple memory accesses, and the inefficiency of huge page sizes consuming significant physical memory.
Innovation Solution
A memory device with a processing unit that receives a memory access request with a first physical address based on a huge page size, translates it into a second physical address based on a smaller normal page size, and accesses memory cells using the second physical address, thereby reducing TLB pressure and physical memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level paging is used to reduce physical memory consumption, then physical memory usage is reduced, but system performance deteriorates due to multiple memory accesses in page table walks
Solution Approach 1:
The patent segments the page table into hierarchical levels (first-level page table and second-level page tables), where the first-level page table stores only partial translation information and points to multiple second-level page tables. This segmentation reduces the size of any single page table structure while maintaining complete address translation capability, thereby reducing physical memory consumption without requiring full page table walks for every translation.
Solution Approach 2:
The patent implements a translation lookaside buffer (TLB) that pre-caches frequently used virtual-to-physical address translations. By performing address translation in advance and storing results in the TLB, the system avoids repeated page table walks for common address translations, thus improving system performance while maintaining the memory efficiency of multi-level paging.
2Device complexity
If a single-level page table is used for all virtual pages, then address translation is simplified, but physical memory is consumed significantly reducing available space for data and programs
Solution Approach 1:
The patent divides the single large page table into multiple smaller page tables organized in a hierarchy. The first-level page table contains entries for different virtual address ranges, each pointing to a corresponding second-level page table. This segmentation reduces the memory footprint of individual page tables while maintaining the simplicity of direct address translation through the hierarchical structure.
Solution Approach 2:
The patent introduces a hierarchical dimension to the page table structure, organizing page tables in multiple levels rather than a single flat structure. This dimensional change allows the system to manage large virtual address spaces by distributing page table entries across multiple levels, reducing the memory consumption at any single level while preserving translation efficiency.
3Productivity
If huge page size is used for memory allocation, then memory allocation efficiency is improved, but TLB pressure increases and physical memory is consumed excessively
Solution Approach 1:
The patent segments huge pages into smaller normal-sized pages within the hierarchical page table structure. The first-level page table entries can point to second-level page tables that manage smaller page units, allowing the system to allocate memory in flexible sizes. This enables efficient memory allocation for large memory needs while maintaining the ability to use smaller page granules when appropriate, thereby reducing excessive physical memory consumption.
Solution Approach 2:
The patent implements dynamic page size selection where the system can choose between huge pages and normal pages based on workload requirements. The hierarchical page table structure allows flexible switching between different page sizes, enabling the system to use huge pages for large contiguous memory allocations when beneficial for allocation efficiency, while falling back to normal pages for smaller or more granular allocation needs, thus avoiding excessive physical memory consumption.
Data Source
AI summary
A memory system includes a host and a memory device. The host is configured to translate a virtual address into first physical address based on a first page size and issue a memory access request including the first physical address. The memory device is configured to receive the memory access request from the host, translate the first physical address into a second physical address based on a second page size that is smaller than the first page size in response to the memory request, and access memory cells using the second physical address.