Memory Device Address Translation for Wear Leveling
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Solution Overview
Problem
Conventional storage devices face inefficiencies in read/write times and management due to varying physical characteristics, particularly in magnetic disk drives, where temporal and spatial locality are not adequately leveraged for optimized data access and wear leveling.
Innovation Solution
A memory device incorporating a non-volatile flash memory with an address translation memory that translates external physical addresses into internal addresses for efficient page access, and a data memory divided into logic groups for wear leveling, using statistical information to manage write cycles and optimize data exchange between groups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional magnetic disk drive is used for data storage, then data can be stored, but read/write time is long (several milliseconds per kilobyte) and varies due to arm arrival time differences
Solution Approach 1:
The storage system is segmented into multiple components: volatile memory for fast access, non-volatile memory for persistent storage, and buffer memory for intermediate data holding. This segmentation allows different types of operations to occur in parallel, reducing overall access time and variability.
Solution Approach 2:
A buffer memory is introduced as an intermediary between the host/processor and the non-volatile memory. The buffer temporarily holds data during transfers, enabling overlapping of read/write operations with address translation and memory access operations, thereby reducing access time variation.
2Productivity
If buffer memory is used to exploit temporal locality, then frequently accessed data can be cached, but device complexity increases
Solution Approach 1:
The buffer memory serves multiple functions: it acts as a cache for temporal locality exploitation, a staging area for data transfers between volatile and non-volatile memory, and a coordination point for address translation operations. This multi-functionality improves productivity without proportionally increasing complexity.
3Speed
If address translation memory is implemented to translate external physical addresses to internal addresses, then page access efficiency is improved, but device complexity increases
Solution Approach 1:
Address translation is performed in advance and the translated addresses are cached in the address translation memory. This preliminary action allows subsequent page accesses to use the pre-computed internal addresses directly, improving access speed while the translation overhead is amortized over multiple accesses.
4Reliability
If data is stored in non-volatile flash memory with block structure, then data persistence is achieved, but garbage collection becomes complex and time-consuming
Solution Approach 1:
The buffer memory serves as an intermediary that facilitates efficient garbage collection by temporarily holding data during block erasure operations and coordinating the movement of valid data to new locations, simplifying the garbage collection process while maintaining data persistence.
5Reliability
If wear leveling is implemented to distribute write cycles evenly, then memory reliability is improved, but management complexity increases
Solution Approach 1:
The system monitors write cycle counts and uses this feedback information to dynamically adjust data placement decisions. By tracking usage patterns and redistributing data based on accumulated write cycle information, the system achieves wear leveling while managing complexity through systematic feedback-driven control.
Data Source
AI summary
A memory device includes a plurality of blocks, and the plurality of blocks may include a plurality of pages. The memory device may translate an external physical address into internal physical address using a non-volatile address translation memory. The memory device may access one page of a plurality of pages using the internal physical address.