Semiconductor Memory Device Asymmetric Plug Pillar Spacing
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Solution Overview
Problem
The existing semiconductor memory devices face reliability issues due to the potential for short circuits between the row decoder and select gate lines and the semiconductor substrate, particularly when contact plugs are inclined, leading to electrical connections via dummy pillars.
Innovation Solution
The configuration includes a memory pillar with a first plug electrically connected to the lowermost wiring layer and a second plug connected to a higher wiring layer, with the distance between the center of the first plug and its adjacent pillar being greater than the distance between the center of the second plug and its adjacent pillar, preventing contact and thus avoiding electrical connection even when the plugs are inclined.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact plugs are used to connect wiring layers, then electrical connection is achieved, but short circuits may occur between row decoder and select gate lines when plugs are inclined
Solution Approach 1:
The patent applies asymmetry by making the distance between the first plug and first pillar greater than the distance between the second plug and second pillar. This asymmetric design ensures that even when plugs are inclined during formation, the larger gap at the first plug position prevents contact with the first pillar, thereby avoiding short circuits between the row decoder and select gate lines.
Solution Approach 2:
The patent implements preliminary anti-action by pre-establishing a safety margin through the asymmetric distance configuration before any inclination occurs. The greater distance between the first plug and first pillar is designed in advance to counteract the potential harmful effect of plug inclination, preventing short circuits before they can occur.
2Ease of manufacture
If uniform distance is maintained between plugs and pillars, then manufacturing is simplified, but inclination causes contact and short circuits
Solution Approach 1:
The patent deliberately introduces asymmetry into the distance configuration between plugs and pillars. Instead of maintaining uniform distances, the first distance (between first plug and first pillar) is made greater than the second distance (between second plug and second pillar). This asymmetric design maintains manufacturing feasibility while effectively preventing short circuits caused by plug inclination.
3Reliability
If distance between first plug and first pillar is increased, then short circuit prevention is improved, but device area increases
Solution Approach 1:
The patent applies local quality by selectively increasing the distance only where needed - specifically between the first plug and first pillar in the row decoder region. The distance between the second plug and second pillar remains smaller. This localized adjustment provides short circuit prevention exactly where the risk exists without unnecessarily expanding the overall device area.
Data Source
AI summary
A semiconductor memory device includes first and second wiring layers above a semiconductor substrate, a memory pillar extending through the first and second wiring layers, a first plug contacting the first wiring layer, a second plug contacting the second wiring layer, a first pillar adjacent to the first plug and extending through the first wiring layer, and a second pillar adjacent to the second plug and extending through the first and second wiring layers. The memory pillar includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and a third insulating layer, a charge storage layer, and a fourth insulating layer on a side surface of the second semiconductor layer. The distance between the center of the first plug and the center of the first pillar is greater than the distance between the center of the second plug and the center of the second pillar.