Semiconductor Memory Device Alternating Bank Group Data Output
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently and reliably reading data from multiple memory regions, requiring improved techniques for gapless input of read control signals and output of data from these regions.
Innovation Solution
A semiconductor memory device and operating method that alternately outputs read data from different bank groups based on predetermined burst sequences, using a scheduler and output driver to manage read control signals and generate scheduling signals for efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If read data are alternately outputted from different bank groups, then data output efficiency is improved, but read burst sequence information may not be accurately reflected
Solution Approach 1:
A read scheduling signal is introduced as an intermediary between the alternating data output from different bank groups and the burst sequence information. This scheduling signal carries and reflects the burst sequence information for each bank group, ensuring that the alternating output mode does not lose the burst sequence information. The scheduling signal acts as a mediator that preserves the relationship between bank groups and their respective burst sequences while enabling efficient alternating data output.
2Speed
If read control signals are inputted gapless, then data reading speed is improved, but control signal management becomes more complex
Solution Approach 1:
Multiple read control signals for different bank groups are merged into a unified scheduling mechanism. The read scheduling signal consolidates the control information for alternating data output from multiple bank groups, allowing gapless input of read control signals while simplifying the management complexity through unified scheduling rather than separate control for each bank group.
Data Source
AI summary
A semiconductor memory device includes a memory region including a plurality of memory blocks, and suitable for outputting first and second read data from first and second memory blocks among the plurality of memory blocks based on first and second read control signals and a read address signal; a scheduler suitable for outputting a read scheduling signal based on the first and second read control signals; and an output driver suitable for outputting the first and second read data by a predetermined burst length alternately twice or more to a data pad based on a mode signal, wherein the first read data are outputted to the data pad according to a first burst sequence, and the second read data are outputted to the data pad according to a second burst sequence, based on the read scheduling signal.