Semiconductor Memory Device Standby Current Reduction

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Solution Overview

Problem

Conventional semiconductor memory devices, such as mask ROM, experience high standby current due to leakage between S and D in memory cells, especially under low power source voltage conditions, leading to increased power consumption.

Innovation Solution

A semiconductor memory device design that applies a bias voltage between the terminals of selected memory cells during reading and not during standby, using complementary potentials to prevent leakage current, thereby suppressing standby current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If pre-charge level is applied to the bit line during standby for reading, then the bit line is ready for rapid reading operation, but leak current is generated due to leak between S and D in memory cells, causing increased standby current

Engineering Contradiction:

Improvereading velocityVSAvoidstandby current

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent applies different voltage levels to different parts of the memory cell terminals. Specifically, the bit line terminal is held at pre-charge level while the source terminal is held at a different potential (ground or intermediate level), creating a local potential difference that prevents leakage current flow during standby while maintaining readiness for rapid reading operations

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent dynamically adjusts the voltage applied to the source terminal based on the operational state. During standby, the source terminal is held at a specific potential to prevent leakage, while during reading operations, the voltage is adjusted to enable proper data readout. This dynamic voltage adjustment resolves the contradiction between maintaining readiness and preventing leakage

Inventive Principle:

Principle #15Dynamics

2Duration of action of moving object

If pre-charge level is applied to the bit line during standby, then the bit line can rapidly transition to reading mode, but the leak current between S and D increases under low power source voltage conditions

Engineering Contradiction:

Improvestandby durationVSAvoidpower consumption

Core Design Contradiction:

Duration of action of moving objectVSLoss of energy

Solution Approach 1:

The patent changes the voltage parameter at the source terminal during standby conditions. By holding the source terminal at a specific voltage level (different from the pre-charge level at the bit line terminal), the patent creates a potential barrier that prevents leakage current flow, thereby reducing power consumption during extended standby periods while maintaining the ability to rapidly transition to reading mode

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS7663923B2Semiconductor memory device and control method thereof

Publication Date: 2010.02.16 MONTEREY RESEARCH LLC

AI summary

This invention provides a semiconductor memory device in which standby current is suppressed to a small level. A ROM device includes memory cells for reading data corresponding to impedance between a terminal connected to bit lines and a source terminal and source power lines connected to the source terminal. In this ROM device, bias voltage is applied between the terminals of selected memory cells.