Memory Device Bitwise Partial Writes Without a Data Mask Pin
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Solution Overview
Problem
Existing memory systems face performance degradation due to the high number of partial write operations, which are inefficient when the memory device lacks a data mask pin, leading to increased latency and power consumption.
Innovation Solution
A memory system and device that perform partial write operations internally through bit operations, using reset and set write commands and data, without relying on a data mask pin, by generating seed data and performing logic operations to update specific bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If partial write operations are performed using read-modify-write commands, then data can be updated in memory cells, but performance degradation occurs due to the large number of operations required
Solution Approach 1:
The patent applies preliminary action by pre-calculating the XOR result of read data and reset write data to generate seed data before the actual write operation. This preparation step allows the memory device to perform only a single XOR operation with set write data during the write phase, rather than performing multiple read-modify-write cycles, thereby reducing overall operation latency and improving productivity.
2Device complexity
If partial write operations are performed without a data mask pin, then device complexity is reduced, but the memory controller must handle all data transmission increasing power consumption
Solution Approach 1:
The patent extracts the data masking function from the physical data mask pin and implements it through logical operations within the memory device. By generating seed data through XOR operations and using this seed data to mask subsequent write operations, the system removes the need for a dedicated data mask pin while maintaining the partial write capability, thus reducing device complexity without significantly increasing power consumption.
3Ease of operation
If all data is transmitted between memory controller and memory device, then partial write operations can be performed, but latency increases due to unnecessary data transmission
Solution Approach 1:
The patent applies local quality by performing the XOR operation locally within the memory device using the read data and reset write data to generate seed data. This local computation allows the system to identify and update only the specific bits that need to be changed, rather than transmitting and processing entire data chunks, thereby reducing data transmission latency while maintaining partial write capability.
4Manufacturing precision
If multiple read-modify-write operations are executed, then data can be modified, but the number of operations increases leading to performance degradation
Solution Approach 1:
The patent merges multiple read-modify-write operations into a single optimized write operation. By pre-calculating the XOR result to generate seed data and then performing a single XOR operation with set write data during the write phase, the system achieves the same data modification accuracy as multiple sequential operations but with significantly improved throughput and reduced operation count.
Data Source
AI summary
A memory system includes a controller configured to transmit a reset write command and reset write data, and transmit a set write command and set write data; and at least one memory device configured to generate seed data by performing a first operation on the reset write data and read data read out from a target memory area in response to the reset write command, generate write data by performing a second operation on the seed data and the set write data in response to the set write command, and write back the write data to the target memory area.