Semiconductor Memory Device Parasitic Capacitance Balancing
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in accurately reading data due to differences in parasitic capacitance between main bit lines and complementary main bit lines, leading to potential inaccuracies in data retrieval.
Innovation Solution
The semiconductor memory device employs a hierarchical bit line structure with selection transistors and selector line driving circuits to match the parasitic capacitance of main bit lines with those of reference bit lines, ensuring equal total parasitic capacitance for accurate data reading by connecting sub-bit lines from different sectors to main bit lines and reference bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sub-bit line from a different sector is connected to the complementary main bit line to balance parasitic capacitance, then the total parasitic capacitance of the main bit line and complementary main bit line become equal, but the number of word lines in the sector becomes an odd number which is inconvenient for users
Solution Approach 1:
The patent introduces a capacitor element as an intermediary component to balance the parasitic capacitance between the main bit line and complementary main bit line. Instead of connecting a sub-bit line from a different sector (which would change the word line count), the capacitor element is inserted between the main bit line and ground, providing the necessary capacitance balancing without affecting the word line structure or user convenience.
Solution Approach 2:
The patent changes the capacitance parameter by adding a capacitor element with a specific capacitance value. This capacitor element is designed to provide exactly the amount of capacitance needed to balance the parasitic capacitance difference, thereby maintaining equal total capacitance on both bit lines while preserving the original word line configuration.
2Reliability
If the parasitic capacitance of the sub-bit line connected to the reference cell is made smaller to balance total parasitic capacitance, then data can be read accurately, but the number of word lines becomes an odd number which is impractical
Solution Approach 1:
The capacitor element serves as an intermediary that provides the necessary capacitance balancing function without requiring changes to the sub-bit line connections or word line configuration. This allows the system to achieve equal total parasitic capacitance while maintaining an even number of word lines per sector.
Solution Approach 2:
The patent extracts the capacitance balancing function from the sub-bit line connection structure and implements it separately through a dedicated capacitor element. This separation allows the word line configuration to remain unchanged (with an even number of word lines) while still achieving the necessary capacitance balance for accurate data reading.
Data Source
AI summary
A semiconductor memory device includes a selector line selection circuit for selecting, in a read operation, a selector line for connecting a first main bit line connected to the sense amplifier with a sub-bit line to which the memory cell being read is connected, a selector line for connecting the first main bit line with a sub-bit line of at least one sector different from the sector to which the memory cell being read belongs, a selector line for connecting a second main bit line connected to the sense amplifier with a sub-bit line to which the reference cell is connected, and a selector line for connecting the second main bit line with a sub-bit line of at least one sector different from the sector to which the memory cell being read belongs.