Semiconductor Memory Device Channel Precharge Voltage Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in improving operation performance and reliability, particularly during data write operations in three-dimensional NAND memory structures, where channel precharge operations can lead to erroneous writes due to voltage differences and capacitance coupling effects.
Innovation Solution
The semiconductor memory device employs a controlled voltage application sequence, including channel precharge operations from the source line side, where the well line and select gate line voltages are managed to stabilize the channel voltage, ensuring the select gate transistor is turned off reliably before program operations, thereby preventing erroneous writes and enhancing memory cell reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If channel precharge operation is performed from source line side, then reliability of memory cell is improved, but operation time is increased
Solution Approach 1:
The patent applies preliminary action by performing channel precharge operation from the source line side before the main program operation. This precharge step stabilizes the channel voltage in advance, preventing erroneous writes during subsequent programming operations, thereby improving reliability without significantly extending total operation time
Solution Approach 2:
The patent employs dynamic voltage control by adjusting well line and select gate line voltages during the precharge operation. This dynamic management of voltage levels optimizes the channel stabilization process, achieving reliable memory cell operation while minimizing the time required for precharge
2Manufacturing precision
If controlled voltage application sequence is used, then manufacturing precision is improved, but device complexity is increased
Solution Approach 1:
The patent segments the voltage application process into distinct controlled stages: channel precharge phase with specific well line and select gate line voltage sequences, and program operation phase. This segmentation allows precise control of voltage timing and levels for each stage, improving manufacturing precision while managing complexity through modular control
Solution Approach 2:
The patent utilizes parameter changes by varying voltage levels and application timing of well line and select gate line during different operation phases. This parameter control enables precise voltage application sequences that improve manufacturing precision without requiring overly complex circuitry, as the changes follow predictable patterns
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a well voltage control circuit, and a source voltage control circuit. Before writing data, first and second transistors respectively connected to a select gate line and a word line are turned on at a first timing, and a ground voltage is applied to the first transistor at a second timing and to the second transistor at a third timing. The source voltage control circuit applies a first voltage to the source line at a fourth timing that is simultaneous with or after the first timing and before the second timing, and the well voltage control circuit applies the first voltage to the well region at a fifth timing that is simultaneous with or after the first timing and before the second timing, and applies a ground voltage to the well region at a sixth timing that is after the fifth timing.