Memory Device Clock Phase Adjustment for Merge Failures
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Solution Overview
Problem
In memory devices, the existing methods for sharing and using data lines during compression read operations can lead to merge failures due to phase differences in clock signals across memory banks.
Innovation Solution
The memory device incorporates a plurality of memory planes, compressing circuits, first merge circuits, second merge circuits, and an output buffer circuit to perform compression read operations efficiently, merging data across memory banks while adjusting clock signals to minimize phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data lines are shared among multiple memory banks through time division, then the number of data lines can be reduced, but merge failures occur due to phase differences in clock signals
Solution Approach 1:
The patent applies preliminary action by adjusting the clock signal phases in advance before data merging occurs. The phase adjustment is performed proactively to prevent merge failures that would otherwise occur during the compression read operation, ensuring that data from multiple memory banks can be reliably merged without errors.
Solution Approach 2:
The patent changes the phase parameter of clock signals to resolve the contradiction. By adjusting the phase of clock signals supplied to different memory banks, the system enables reliable data merging while maintaining the shared data line configuration, thus reducing the total number of data lines required.
2Productivity
If compression read operations are performed simultaneously across multiple memory banks, then productivity is improved, but merge failures occur due to clock signal phase differences
Solution Approach 1:
The system performs preliminary phase adjustment of clock signals before initiating simultaneous compression read operations across multiple memory banks. This ensures that when data is read simultaneously from multiple banks and merged, the clock signals are already synchronized to the correct phases, preventing merge failures and maintaining data merging accuracy.
Solution Approach 2:
The patent adjusts the phase parameter of clock signals supplied to different memory banks to enable simultaneous compression read operations without merge failures. By changing the clock signal phases appropriately, the system achieves both high productivity through simultaneous operations and high reliability through accurate data merging.
3Device complexity
If clock signals are supplied to multiple memory banks without phase adjustment, then device complexity is reduced, but merge failures occur during data merging
Solution Approach 1:
The patent introduces phase adjustment of clock signals supplied to multiple memory banks. By changing the phase parameter of clock signals, the system enables reliable compression read operations and data merging while maintaining relatively simple device architecture. The phase adjustment can be implemented through straightforward circuit modifications without significantly increasing overall device complexity.
Data Source
AI summary
A memory device includes: a plurality of memory planes each including a plurality of memory banks, the plurality of memory planes being grouped into memory planes; a plurality of compressing circuits respectively connected to the plurality of memory banks, the plurality of compressing circuits outputting compressed data by respectively compressing data read from the plurality of memory; a plurality of first merge circuits receiving the compressed data and output control signals corresponding to at least a portion of the memory banks, the plurality of first merge circuits outputting first merged data obtained by merging compressed data corresponding to memory banks grouped as a first merge group; a second merge circuit outputting second merged data obtained by merging first merged data generated from memory banks included in the same plane group; and an output buffer circuit outputting the second merged data, based on at least a portion of the output control signals.