Memory Device Coarse-Fine Programming for Fast, Accurate Reads

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Solution Overview

Problem

Existing semiconductor memory devices face challenges in accurately reading data without errors, particularly when only a coarse program operation is performed, leading to wide threshold voltage distributions and increased error rates.

Innovation Solution

A two-step program operation is implemented, consisting of a fine program operation followed by a coarse program operation, allowing for error detection and correction during the first step, enabling faster programming and improved read performance without waiting for the second step to complete.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If only a coarse program operation is performed, then program speed is improved, but read accuracy deteriorates due to wide threshold voltage distributions

Engineering Contradiction:
Improveprogram speedVSAvoidread accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent segments the programming process into two distinct operations: a coarse program operation that quickly establishes initial threshold voltage distributions, and a fine program operation that precisely refines these distributions. This segmentation allows the system to achieve both fast programming (through the coarse operation) and high read accuracy (through the fine operation), resolving the contradiction between speed and reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The coarse program operation serves as a preliminary action that rapidly forms initial threshold voltage distributions before the fine program operation refines them. By performing this preliminary coarse programming, the system can quickly prepare memory blocks for subsequent precise programming, improving overall program speed while maintaining the ability to achieve accurate final states

Inventive Principle:
Principle #10Preliminary action

2Reliability

If a two-step coarse-fine program operation is performed, then read accuracy is improved, but program speed deteriorates

Engineering Contradiction:
Improveread accuracyVSAvoidprogram speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent implements dynamic adaptation by monitoring read accuracy after the coarse program operation and selectively applying the fine program operation only when necessary. This dynamic approach adjusts the programming process based on actual performance needs, maintaining high read accuracy while avoiding unnecessary fine programming operations that would slow down the overall process

Inventive Principle:
Principle #15Dynamics

3Manufacturing precision

If the fine program operation is performed, then threshold voltage distribution precision is improved, but processing time increases

Engineering Contradiction:
Improvethreshold voltage distribution precisionVSAvoidprocessing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The system performs self-service by automatically evaluating whether the coarse program operation has achieved sufficient threshold voltage distribution precision. When the coarse operation is adequate, the system skips the fine program operation entirely, allowing the memory block to serve itself without requiring additional time-consuming refinement steps

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP4181140B1Memory device, memory system, and method of operating the memory system
Publication Date: 2025.08.20 SAMSUNG ELECTRONICS CO LTD
  • EP4181140B1 patent drawingFigure 1
  • EP4181140B1 patent drawingFigure 2A
  • EP4181140B1 patent drawingFigure 2B

AI summary

A method of operating a memory system includes programming, in a memory device, K logical pages stored in a page buffer circuit into a memory cell array, reading, from the memory device, the K logical pages programmed into the memory cell array into the page buffer circuit after a first delay time elapses, transmitting, in a memory controller, N-K logical pages to the memory device, and programming, in the memory device, N logical pages into the memory cell array based on the read K logical pages and the N-K logical pages, wherein K is a positive integer and N is a positive integer greater than K.