Memory Device Column Repair Segmentation
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Solution Overview
Problem
The increasing number of redundant memory cells required for column repair in semiconductor memory devices leads to increased chip area and decreased efficiency and productivity, as more redundant cells are needed to replace defective cells, thereby expanding the spare area and reducing the overall effectiveness of memory devices.
Innovation Solution
The memory device incorporates a column repair controller that maps defective cell addresses to redundant cell addresses, allowing for efficient replacement of defective cells within the existing memory cell array, reducing the need for additional redundant cells by dividing page buffer groups into repair groups, thereby minimizing the spare area and chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of column lines corresponding to a column repair unit increases, then the repair capability is improved, but the number of redundant memory cells required increases, leading to increased chip area
Solution Approach 1:
The memory device divides the page buffer groups into multiple repair groups, where each repair group is associated with a specific column repair unit. This segmentation allows the system to handle column repairs in smaller, manageable units rather than requiring redundant cells for the entire column repair unit, thereby reducing the chip area while maintaining repair capability.
Solution Approach 2:
The patent introduces a hierarchical organization where repair groups are nested within column repair units. By adding this intermediate level of organization, the system can map defective cells to redundant cells within the same repair group rather than requiring a direct mapping across the entire column repair unit, reducing the number of redundant cells needed.
2Reliability
If the number of redundant memory cells increases, then the column repair capability is improved, but the efficiency and productivity decrease
Solution Approach 1:
By segmenting the column repair functionality into multiple column repair units with associated repair groups, the system achieves reliable column repair capability without requiring a large number of redundant memory cells. Each repair group handles a subset of column lines, allowing efficient repair operations with minimized redundant cell overhead.
Solution Approach 2:
The patent changes the organizational parameters of the memory device by introducing repair groups as an intermediate structure between page buffer groups and column repair units. This parameter change optimizes the ratio of functional memory cells to redundant memory cells, improving productivity while maintaining repair capability.
3Reliability
If the spare area is expanded to accommodate more redundant memory cells, then the column repair capability is improved, but the overall effectiveness of the memory device is reduced
Solution Approach 1:
The memory device is segmented into multiple column repair units, each with its own repair group. This segmentation allows the spare area to be efficiently utilized by distributing redundant memory cells across multiple repair groups rather than concentrating them in a single large spare area, thereby maintaining repair capability while preserving overall device effectiveness.
Solution Approach 2:
The patent optimizes the parameters of the memory device by introducing repair groups with a specific number of page buffer groups. This parameter optimization ensures that the spare area is adequately sized to provide column repair capability while minimizing the impact on the overall effectiveness and productivity of the memory device.
Data Source
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AI summary
A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.