Memory Device Column Select Line Grouping for Wiring Complexity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complexity of wiring in semiconductor memory devices, particularly with numerous and complex column select lines on one side of the memory cell array, increases chip size and design difficulty, especially when trying to reduce the area occupied by logic circuits of address decoders.
Innovation Solution
The memory device reduces the number of wires connected to second address decoders by dividing column select lines into groups, each assigned to a corresponding second address decoder, thereby reducing the wiring area and complexity, and allows for a more compact design by positioning first and second address decoders on the same side of the memory bank.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If all address decoders are disposed on the same side of the memory cell array to reduce chip size, then the chip size is effectively reduced, but the wiring becomes numerous and complex making it difficult to plan the circuit structure
Solution Approach 1:
The patent divides the column select lines into multiple groups (first group, second group, third group, fourth group) and assigns each group to a corresponding second address decoder. This segmentation reduces the number of wires connected to each individual decoder, simplifying the wiring complexity while maintaining the compact layout with all decoders on one side of the memory cell array.
2Device complexity
If the number of wires connected to second address decoders is reduced to simplify wiring, then the area occupied by logic circuits is reduced, but the ability to access all memory cells may be compromised
Solution Approach 1:
The column select lines are segmented into four groups, with each group assigned to a dedicated second address decoder. This ensures that all memory cells remain accessible while reducing the wire count per decoder. The segmentation maintains full functionality by distributing the access capability across multiple decoders working in parallel.
Solution Approach 2:
Multiple second address decoders are used, each capable of decoding its assigned group of column select lines. This multi-functional approach ensures that the system as a whole can access all memory cells, while each individual decoder handles a manageable subset, reducing wiring complexity.
3Area of stationary object
If the area occupied by logic circuits of address decoders is reduced to decrease chip size, then the chip size is reduced, but the wiring planning becomes more difficult
Solution Approach 1:
By segmenting the column select lines into groups and assigning them to different second address decoders, the patent reduces the number of wires each decoder must handle. This makes wiring planning more manageable and easier to manufacture, while still achieving compact chip size with all decoders positioned on one side of the memory cell array.
Data Source
AI summary
A memory device is provided. The memory device includes at least one memory bank, at least one first address decoder set, and at least one second address decoder set. Each of the at least one memory bank includes a plurality of memory cell arrays. Each of the at least one second address decoder set includes a plurality of second address decoders. The at least one second address decoder set receives a plurality of column select lines to perform an access operation on memory cells of the memory cell arrays. The column select lines are divided into a plurality of column select line groups, and each of the column select line groups is assigned to the second address decoder corresponding thereto, wherein the number of the column select lines allocated to each of the column select line groups is less than a total number of the column select lines.