Memory Device Command Bus Training via Divided Clock Signals
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Solution Overview
Problem
Existing memory device and system technologies face challenges in accurately capturing command/address signals and chip selection signals at high clock frequencies, leading to difficulties in command bus training, which is crucial for high-speed data transmission.
Innovation Solution
A method is introduced where a memory device generates internal clock signals by dividing the received clock signal, allowing for adjustable delays in chip selection signals, and compares these signals with the original command/address signals to determine optimal timing, thereby improving the accuracy of command bus training.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock signal frequency is increased to support high-speed data transmission, then the data transmission speed is improved, but the accuracy of capturing command/address signals and chip selection signals deteriorates
Solution Approach 1:
The patent divides the clock signal into multiple divided clock signals with different frequencies (e.g., first divided clock signal at 1/2 frequency, second divided clock signal at 1/4 frequency). This segmentation allows the system to use different clock frequencies for different functions: higher frequency for data transmission and lower frequency for accurate signal capture and timing synchronization.
Solution Approach 2:
The patent dynamically switches between different divided clock signals based on the operational phase. During command bus training mode, the system uses the second divided clock signal (lower frequency) for accurate timing. During normal operation, it switches to the first divided clock signal or original clock signal for high-speed data transmission. This dynamic adaptation resolves the contradiction between speed and accuracy.
2Speed
If the clock signal frequency is increased to support high-speed data transmission, then the data transmission speed is improved, but the command bus training accuracy deteriorates
Solution Approach 1:
The patent segments the clock signal into multiple divided versions, using the second divided clock signal (at 1/4 frequency) specifically for command bus training operations. This lower frequency provides sufficient time margins for accurate timing setup and verification during training, while the first divided clock signal (at 1/2 frequency) supports high-speed operation.
Solution Approach 2:
The patent performs command bus training before normal data transmission using the second divided clock signal. This preliminary action at a lower frequency ensures that timing parameters are properly established and verified before switching to higher frequency operations, thereby guaranteeing training accuracy.
3Measurement precision
If multiple divided clock signals are generated and multiple signals are transmitted and compared during training, then the training accuracy is improved, but the training process complexity increases
Solution Approach 1:
The patent uses the data bus to serve multiple functions: it transmits both the first command/address signal from the memory controller and the second command/address signal from the memory device. This multi-functionality eliminates the need for separate dedicated training signal lines, reducing overall system complexity while maintaining high training accuracy through multi-signal comparison.
Data Source
AI summary
A memory device and system supporting command bus training are provided. An operating method of the memory device includes entering into a command bus training mode, receiving a clock signal, a chip selection signal and a first command/address signal, generating an internal clock signal by dividing the clock signal, generating a second command/address signal by latching the first command/address signal at a rising edge or a falling edge of the internal clock signal when a chip selection signal is activated, and outputting the second command/address signal.