Memory Device Implicit Ordering for Overlapping Command Execution

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Solution Overview

Problem

Existing memory systems face inefficiencies in handling ordered and simple commands, leading to prolonged command execution times due to strict ordering requirements and potential overlap in command execution.

Innovation Solution

Implementing a system that determines the implicit ordering of commands based on their attributes, allowing for simultaneous execution of certain commands without overlap, thereby reducing overall execution duration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If strict ordering requirements are enforced for all commands, then command execution reliability is improved, but command execution time increases

Engineering Contradiction:
Improvecommand execution reliabilityVSAvoidcommand execution time
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent segments commands into two distinct types: ordered commands and simple commands. This segmentation allows the system to apply different execution rules to different command categories, enabling overlapping execution of simple commands while maintaining strict ordering for ordered commands, thus resolving the contradiction between reliability and execution time

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces dynamic command handling where the execution behavior changes based on command attributes. The system determines whether a command is ordered or simple based on its characteristics, and adjusts execution strategy accordingly - allowing simple commands to overlap with ongoing operations while ensuring ordered commands maintain their sequence, thereby optimizing both reliability and time

Inventive Principle:
Principle #15Dynamics

2Reliability

If all commands are executed sequentially without overlap, then command execution reliability is improved, but productivity decreases

Engineering Contradiction:
Improvecommand execution reliabilityVSAvoidcommand execution throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By segmenting commands into ordered and simple categories, the system can execute simple commands in parallel with ongoing operations while maintaining sequential execution for ordered commands. This segmentation enables overlapping execution patterns that improve throughput without compromising the reliability of critical ordered operations

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different execution quality characteristics to different command types locally. Simple commands benefit from overlapping execution and relaxed timing constraints to improve productivity, while ordered commands receive strict sequential enforcement to maintain reliability, thus optimizing both metrics simultaneously

Inventive Principle:
Principle #3Local quality

3Productivity

If command attributes are analyzed to determine implicit ordering, then command execution efficiency is improved, but device complexity increases

Engineering Contradiction:
Improvecommand execution efficiencyVSAvoidcommand handling complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent performs preliminary analysis of command attributes during the command reception phase to determine whether a command is ordered or simple. This preliminary classification enables the system to prepare appropriate execution strategies in advance, improving efficiency while keeping the complexity manageable through clear, rule-based decision logic

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12360698B2Implicit ordered command handling
Publication Date: 2025.07.15 MICRON TECHNOLOGY INC
  • US12360698B2 patent drawing
  • US12360698B2 patent drawing
  • US12360698B2 patent drawing

AI summary

Methods, systems, and devices for improved implicit ordered command handling are described. For instance, a memory device may receive, from a host device, a first command and a second command. The memory device may determine whether a first memory operation associated with the first command and a second memory operation associated with the second command are to be performed in an order relative to each other based on a first time when the first command is received relative to a second time when the second command is received. The memory device may select whether to perform a first memory access procedure or a second memory access procedure based on whether the first memory operation and the second memory operation are a same type of memory operation and on whether the first memory operation and the second memory operation are to be performed in the order relative to each other.