3D Memory Device With Common Source Line
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in increasing integration density due to limitations in the stacking and connection of channel layers and gate structures, which affect the efficiency and capacity of memory cells.
Innovation Solution
The proposed memory device incorporates a substrate with alternately stacked gate electrode layers and channel layers, a gate insulating layer with both vertical and horizontal parts, and a common source line with different heights, allowing for increased integration density by connecting channel layers directly to the substrate and each other through a horizontal channel layer, while maintaining efficient charge storage and insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If channel layers are stacked vertically to increase integration density, then storage capacity improves, but manufacturing complexity and connection difficulty increase
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional vertical stacking, arranging channel layers and gate electrode layers in multiple vertical levels. This dimensional change enables significantly higher integration density by utilizing the vertical space above the substrate, allowing memory cells to be stacked in the third dimension rather than only expanding in the planar direction.
Solution Approach 2:
The patent implements a nested structure where gate insulating layers are positioned between and surround channel layers, with gate electrode layers alternating with channel layers in a concentric or interlaced arrangement. This nesting enables multiple functional layers to occupy the same vertical space efficiently, increasing the number of memory cells per unit volume while maintaining manufacturability through sequential deposition processes.
2Quantity of substance
If more gate electrode layers and channel layers are stacked, then memory capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary patterning and positioning of sacrificial layers or alignment markers before depositing subsequent gate and channel layers. By pre-establishing reference structures on the substrate, the manufacturing process can maintain consistent alignment across multiple vertical stacking steps, reducing the cumulative precision errors that would otherwise occur with each additional layer deposition.
Solution Approach 2:
The patent utilizes controlled variations in deposition parameters, such as adjusting film thickness, deposition rate, and temperature, to optimize the dimensional control of each stacked layer. By carefully tuning these parameters, the manufacturing process achieves the required precision for thin-layer alignment while maintaining high throughput, enabling the production of multi-layer structures with consistent dimensional tolerances.
3Quantity of substance
If channel layers are connected horizontally to the substrate, then integration density improves, but insulation and charge storage efficiency may deteriorate
Solution Approach 1:
The patent introduces gate insulating layers as intermediary structures between the channel layers and the substrate, and between adjacent channel layers. These insulating layers serve as electrical barriers that prevent unwanted charge leakage while maintaining the vertical connectivity of the memory cell structure. The intermediary insulating layers enable horizontal channel connections to the substrate without compromising the charge storage efficiency of the memory cells.
Solution Approach 2:
The patent employs composite material structures combining conductive channel layers with insulating gate dielectric materials in an alternating stacked configuration. This composite approach allows the channel layers to provide electrical connectivity paths while the insulating layers provide charge isolation and storage functionality, achieving both high integration density through horizontal connections and maintained charge storage efficiency through the insulating barrier properties of the composite structure.
Data Source
AI summary
A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.