Memory Device Compressive Test Method Using Data Output Unit
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Solution Overview
Problem
Conventional memory device testing methods require a large number of interface pads, limiting the ability to test multiple chips simultaneously and increasing testing time and production costs due to the need for extensive equipment and long testing durations.
Innovation Solution
A memory device design that reduces the number of interface pads required by using a data output unit with a selection information generator and line selector to compress and output data from multiple banks through a single interface pad, allowing for sequential or simultaneous output of compressed data from multiple banks during a compressive test.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional compressive test method is used to test each cell individually, then testing reliability is ensured, but testing time becomes long and production cost increases
Solution Approach 1:
The patent merges data from multiple banks into a single compressed data stream that is output through one interface pad. The data output unit combines compressed data from first and second banks, allowing parallel testing of multiple chips simultaneously while maintaining reliability through comprehensive cell testing.
Solution Approach 2:
The patent transitions from a traditional one-to-one mapping between interface pads and banks to a many-to-one mapping where multiple banks share a single interface pad. This dimensional change in data output architecture enables time multiplexing of data from different banks through the same pad, reducing the total number of pads needed.
2Productivity
If many banks are activated simultaneously for compressive test, then testing speed increases, but number of interface pads required increases
Solution Approach 1:
The data output unit merges compressed data from multiple activated banks into a single data stream for output through one interface pad. This combining mechanism allows the system to activate many banks simultaneously for high-speed testing while requiring fewer interface pads than the number of banks.
Solution Approach 2:
The single interface pad serves multiple functions by time-multiplexed output of compressed data from different banks. The interface pad universally handles data output for all activated banks through sequential activation controlled by the data output unit, eliminating the need for dedicated pads for each bank.
3Loss of time
If number of interface pads is reduced to test multiple chips simultaneously, then testing time decreases, but data output complexity increases
Solution Approach 1:
The data output unit performs preliminary compression of data from multiple banks before outputting through the single interface pad. By compressing and preparing data in advance from all activated banks, the system simplifies the output process and manages complexity internally while presenting a simple interface to the test equipment.
Solution Approach 2:
The data output unit acts as an intermediary between the multiple activated banks and the single interface pad. It mediates the data flow by receiving compressed data from all banks and systematically outputting them through the shared pad, managing the complexity of multiplexing and timing internally.
4Ease of operation
If conventional test equipment with many interface pads is used, then each chip can be tested independently, but production cost increases
Solution Approach 1:
The patent merges the testing capabilities of multiple chips into a single test operation that outputs compressed data through one interface pad. This allows multiple chips to be tested simultaneously and independently in terms of data processing, while sharing the same physical interface pad, thereby reducing equipment cost.
Solution Approach 2:
The system changes the operational parameters by time-multiplexing data output from multiple banks through a single interface pad. This parameter change in the data output timing and routing allows the same physical pad to serve multiple chips sequentially, maintaining independent testing capability while reducing hardware requirements.
Data Source
AI summary
A memory device includes a first bank, a second bank, a plurality of interface pads, and a data output unit configured to output compressed data of the first bank through at least one interface pad among the plurality of interface pads and subsequently output compressed data of the second bank through the one interface pad.