Semiconductor Memory Device Concurrent Data Output Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently managing data output operations across multiple memory dies, leading to potential collisions and reduced performance due to sequential input and output timing requirements.
Innovation Solution
The semiconductor memory device incorporates a control circuit that executes data-out operations based on trigger signals, allowing for simultaneous data output from multiple memory dies by synchronizing input signals through a controller die, thereby avoiding collisions and optimizing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential input and output timing requirements are used for multiple memory dies, then timing collision avoidance is achieved, but data output efficiency and performance are reduced
Solution Approach 1:
The patent segments the data output process into two independent phases: command input phase and data output phase. During the command input phase, command signals are input to memory dies while data output is held in register arrays. During the data output phase, data is output from register arrays while command input is held. This temporal segmentation allows multiple memory dies to operate simultaneously without timing collisions while maintaining high data output efficiency.
2Productivity
If trigger signals are used to synchronize data-out operations, then concurrent data output from multiple memory dies is enabled, but control circuit complexity increases
Solution Approach 1:
The patent introduces trigger signals as intermediary elements that coordinate between the controller die and memory dies. The trigger signal is generated by the controller die and input to memory dies to synchronize data-out operations. This intermediary mechanism enables concurrent data output from multiple memory dies while keeping the control circuit design relatively simple and manageable through standardized synchronization protocols.
3Productivity
If register arrays are used to hold data during command input, then data output operations can proceed concurrently, but device complexity and resource requirements increase
Solution Approach 1:
The patent applies preliminary action by having memory dies pre-load data into register arrays during the command input phase before the data output phase begins. This allows the data to be ready for immediate output when the trigger signal is received, enabling concurrent operations without requiring complex real-time data buffering mechanisms during the critical data output window.
Data Source
AI summary
A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.