Semiconductor Memory Device Conductive Lines Adjoin Carrier Surface
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Solution Overview
Problem
The challenge is to reduce the size of memory devices while minimizing the space required for wiring without increasing process complexity, as existing technologies face limitations in reducing the size of memory cells due to the need for wiring, contacts, and metallization layers.
Innovation Solution
A non-volatile semiconductor memory device with a memory cell array and peripheral portion, where conductive lines in the peripheral portion and source lines in the array portion are formed using a damascene process, allowing for reduced contact resistance and overlay requirements, and conductive lines are designed to adjoin the semiconductor carrier surface, enabling efficient interconnection and reduced contact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional wiring and metallization layers are used to connect memory cells, then reliable electrical connections are achieved, but the device size increases and packaging density decreases
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional conductive lines that adjoin the semiconductor carrier surface. Conductive lines extend from the surface into the substrate, enabling vertical interconnections that reduce lateral wiring space and allow higher packaging density without increasing device footprint.
Solution Approach 2:
The patent combines the functions of separate contact holes and wiring layers into integrated conductive lines formed by a single damascene process. This merging eliminates the need for distinct contact and interconnect structures, reducing overall device complexity while maintaining reliable electrical connections.
2Area of stationary object
If smaller memory cells are designed to reduce device size, then packaging density increases, but the space required for wiring and contacts becomes insufficient
Solution Approach 1:
By implementing conductive lines that extend vertically from the semiconductor carrier surface into the substrate, the patent provides adequate wiring space without increasing the lateral area of memory cells. This vertical dimension allows sufficient room for contacts and interconnections while maintaining small cell footprints.
3Reliability
If conventional contact structures are used, then reliable electrical connections are achieved, but contact resistance is high and overlay requirements are stringent
Solution Approach 1:
The damascene process enables precise control of conductive line dimensions and positions through sequential deposition and etching steps. This parameter control reduces overlay requirements by allowing self-aligned formation of conductive lines, improving manufacturing precision while maintaining reliable electrical connections with lower contact resistance.
Data Source
AI summary
A memory device having an array portion including memory cells, and a peripheral portion including conductive lines is disclosed. In one embodiment, portions of the conductive lines adjoin a surface of a semiconductor carrier.