Semiconductor Memory Device Plate Electrode Conductor Network
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Solution Overview
Problem
In semiconductor memory devices, the long connection path between the power supply line and the plate electrode of memory capacitors increases connection resistance, leading to malfunctions due to high aspect ratio vias, which affects the proper distribution of electric potential.
Innovation Solution
The semiconductor memory device connects the plate electrodes of memory cell arrays using electrical conductors, such as those formed from tungsten or titanium nitride, to reduce electrical resistance and maintain proper electric potential, preventing malfunctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the connection path between power supply line and plate electrode is made long to reach all memory cell arrays, then all capacitors can be supplied with power, but the connection resistance increases leading to malfunctions
Solution Approach 1:
The patent divides the connection structure into multiple segments by introducing intermediate connection portions (conductive layers) between the power supply line and plate electrodes. Instead of a single long connection path, the path is segmented into multiple shorter sections connected through intermediate conductive layers, reducing overall resistance while maintaining connectivity to all memory cell arrays.
Solution Approach 2:
The patent transitions from a one-dimensional linear connection path to a multi-dimensional network structure. Conductive layers are extended in multiple directions (first and second directions) to create a grid-like connection network, allowing power supply to reach plate electrodes through multiple parallel paths rather than a single long path, thereby reducing resistance.
2Reliability
If conventional connection methods are used with high aspect ratio vias, then manufacturing is simpler, but connection resistance increases causing malfunctions
Solution Approach 1:
The patent introduces intermediate connection portions (conductive layers) that act as mediators between the power supply line and plate electrodes. These intermediate conductive layers provide additional connection points and alternative current paths, reducing the effective connection resistance without requiring changes to the fundamental via manufacturing process.
Solution Approach 2:
The patent merges multiple connection functions into a unified conductive network. Multiple conductive layers are combined to form an integrated connection structure that simultaneously provides multiple parallel current paths, reducing resistance while maintaining manufacturing simplicity through standard layered fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively lowers the electrical resistance between plate electrodes, ensuring proper electric potential distribution and preventing malfunctions in semiconductor memory devices by reducing the connection path length.
Implementation Method 1
The second region includes a conductor, the conductor connecting the third electrodes of the memory cell arrays
Data Source
AI summary
A semiconductor memory device, includes: a first region including a first memory cell array; a second region arranged with the first region; and a third region arranged with the second region and including a second memory cell array. Each memory cell array includes: a field effect transistor above a semiconductor substrate, including a gate, a source, and a drain, the gate being connected to a first wiring, and one of the source and the drain being connected to a second wiring; and a capacitor below the transistor, including a first electrode connected to the other of the source and the drain, a second electrode facing the first electrode, and a third electrode connected to the second electrode and extending to the second region. The second region includes a conductor, the conductor connecting the third electrodes of the memory cell arrays.