3D Stacked Memory Device Semiconductor Connection Protrusion Alignment
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Solution Overview
Problem
Conventional nonvolatile semiconductor memory devices face challenges in increasing memory capacity due to limitations in cost and technology, particularly in reducing element dimensions and improving mask alignment and dimensional accuracy during the manufacturing process.
Innovation Solution
A three-dimensionally stacked memory device configuration is implemented, featuring alternately stacked insulating and electrode films, silicon pillars, and charge storage layers, with a semiconductor connection portion that includes protrusions to enhance alignment accuracy and dimensional precision, allowing for increased productivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If element dimensions are reduced to increase memory capacity, then memory capacity increases, but manufacturing precision and mask alignment accuracy deteriorate
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking of memory cells. Multiple stacks are formed vertically on the substrate, with each stack containing multiple memory cells distributed across different height levels. This dimensional change allows memory capacity to scale vertically rather than requiring continuous reduction of element dimensions, thereby maintaining mask alignment accuracy while increasing overall memory capacity.
2Quantity of substance
If element dimensions are reduced to increase memory capacity, then memory capacity increases, but productivity deteriorates
Solution Approach 1:
By stacking memory cells vertically in three dimensions, the patent increases memory capacity without requiring proportional increases in manufacturing complexity. The collective processing of multiple stacks formed simultaneously improves productivity, as the three-dimensional structure allows for parallel fabrication of multiple memory cells through shared process steps.
3Quantity of substance
If three-dimensionally stacked memory is implemented, then memory capacity increases, but device complexity increases
Solution Approach 1:
The patent divides the three-dimensional memory structure into multiple discrete stacks, where each stack functions as an independent memory cell unit. This segmentation allows for modular fabrication and simplifies the overall device architecture by breaking down the complex three-dimensional structure into manageable repeating units that can be processed collectively.
Solution Approach 2:
The patent employs universal process steps that serve multiple functions simultaneously. For example, single process steps form multiple stacks, create multiple memory cells, and establish electrical connections across different levels. This multi-functionality reduces the total number of fabrication steps required, thereby managing device complexity despite the increased memory capacity.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked structures, first and second semiconductor pillars, first and second memory units, and a semiconductor connection portion. The stacked structures include electrode films and first inter-electrode insulating films alternately stacked in a first direction. The second stacked structure is aligned with the first stacked structure in a second direction perpendicular to the first. The first and second semiconductor pillars pierce the first and second stacked structures, respectively. The first and second memory units are provided between the electrode films and the semiconductor pillar, respectively. The semiconductor connection portion connects the first and second semiconductor pillars and includes: an end connection portion; and a first protrusion having a side face continuous with a side face of the first semiconductor pillar. The semiconductor connection portion does not include a portion smaller than a diameter of the first semiconductor pillar.