Semiconductor Memory Device Contact Array Design
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Solution Overview
Problem
Current semiconductor memory devices face limitations in increasing the center-to-center spacing between adjacent memory elements while maintaining a small memory cell size, which restricts device density and processing efficiency.
Innovation Solution
The memory device design features a staggered array of first level contacts with vacant rows, allowing for the formation of extended second level contacts and memory elements that shift towards vacant regions, thereby increasing the center-to-center distance between memory elements beyond the conventional 2F spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the minimum feature size F is shrunk to increase device density, then device density improves, but the minimum feature pitch 2F also shrinks which limits further scaling and increases photolithography constraints
Solution Approach 1:
The patent introduces a two-level contact structure where second level contacts extend into vacant regions in the vertical dimension, allowing memory elements to be positioned beyond the conventional 2F pitch limit while maintaining compatibility with existing photolithography processes
Solution Approach 2:
The contact structure is segmented into first level contacts arranged in a grid and second level contacts that extend into vacant regions, allowing independent optimization of each level's positioning to achieve greater separation
2Quantity of substance
If the center-to-center spacing between memory elements is reduced to 2F to maximize device density, then device density improves, but processing margins deteriorate and manufacturing becomes more difficult
Solution Approach 1:
By extending second level contacts into vacant regions vertically, the design achieves 2.4F spacing between memory elements, providing 20% additional processing margin while maintaining high device density
3Quantity of substance
If the memory cell size is reduced to 6F2 to increase device density, then device density improves, but the spacing between adjacent memory elements is constrained to minimum 2F which limits performance optimization
Solution Approach 1:
The patent uses vertical extension of second level contacts into vacant regions to achieve 2.4F spacing between memory elements within the 6F2 cell size, providing additional spacing for performance optimization without increasing cell area
Solution Approach 2:
The contact structure uses asymmetric arrangement with every third row vacant, allowing second level contacts to extend preferentially into vacant regions and achieve greater separation in specific directions
Data Source
AI summary
The present invention is directed to a semiconductor memory device including a plurality of first level contacts arranged in an array with every third row vacant along a first direction, thereby forming multiple contact regions separated by multiple vacant regions along the first direction with each of the multiple contact regions including a first row and a second row of the first level contacts extending along a second direction; a first and second plurality of second level contacts formed on top of the first level contacts with the second plurality of second level contacts having elongated shape extending into the vacant regions adjacent thereto; and a first and second plurality of memory elements formed on top of the first and second plurality of second level contacts, respectively, thereby permitting the memory elements to have greater center-to-center distance between two closest neighbors than the first level contacts.