Semiconductor Memory Device Contact Alignment and Insulation
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Solution Overview
Problem
Current semiconductor memory devices face challenges in manufacturing efficiency due to misalignment of contacts, leading to electrical connections with the substrate, which affects voltage application and increases manufacturing costs.
Innovation Solution
The semiconductor memory device design incorporates a specific arrangement of semiconductor films and conductive layers, with a gradual reduction in the number of memory structures as it approaches the contact region, and the use of insulating layers and structures to maintain electrical insulation, reducing the imbalance of electric charge and preventing distortion during the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If contacts are aligned with memory structures in conventional semiconductor memory devices, then manufacturing process is simplified, but electrical connections with substrate occur causing voltage application issues and increased manufacturing costs
Solution Approach 1:
The contact region is segmented into multiple contact holes arranged in a specific pattern, with at least one contact hole positioned offset from the memory structures. This segmentation allows the contact to be divided into multiple parts, preventing direct electrical connection with the substrate while maintaining manufacturing feasibility through standardized hole formation processes.
Solution Approach 2:
The contact holes are arranged asymmetrically relative to the memory structures, with at least one contact hole positioned at an offset location rather than directly aligned with memory structures. This asymmetric arrangement breaks the symmetry that would otherwise allow electrical connection paths to the substrate, ensuring electrical insulation while keeping the manufacturing process relatively simple.
2Reliability
If the number of memory structures is reduced near contact regions, then electrical insulation is improved, but device area utilization decreases
Solution Approach 1:
The memory structure arrangement transitions from a uniform dense pattern in the main memory region to a locally modified pattern near the contact region. Specifically, at least one contact hole is positioned offset from memory structures, creating a local variation in structure density and arrangement. This local quality change ensures electrical insulation at the contact interface while preserving high area utilization in the bulk memory region.
Data Source
AI summary
A semiconductor memory device comprises a substrate, first semiconductor films extending in a first direction crossing a surface of the substrate and arranged in a second direction and in a third direction, a conductive layer which covers peripheral faces of the first semiconductor films on a cross-section crossing the first direction, and a contact which extends in the first direction. Here, when straight lines disposed at equal intervals in the second direction on the cross-section and perpendicular to the second direction are defined as first to third straight lines, a first number of the first semiconductor films are provided on the first straight line, a second number less than the first number of the first semiconductor films are provided on the second straight line, a third number less than the second number of the first semiconductor films are provided on the third straight line.