Memory Device Contact Plug with Spacer for Reduced Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high degree of integration in memory devices leads to thin conductive layer patterns, making it difficult to form contact holes that expose only the upper conductive layer pattern, resulting in high contact resistance between the gate structure and the contact plug, which deteriorates the electrical characteristics of memory devices.
Innovation Solution
A gate structure is formed with a first conductive layer pattern and a second conductive layer pattern stacked on a substrate, where the second conductive layer pattern has a lower resistance, and a contact plug is formed through the second conductive layer pattern with a spacer surrounding its sidewall to directly contact the gate structure, reducing contact resistance. The contact plug includes a metal layer pattern and a barrier layer pattern, and the spacer is made of silicon nitride, with an insulating interlayer covering the gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration is increased to improve memory device capacity, then the conductive layer patterns become thinner, but it becomes difficult to form contact holes that expose only the upper conductive layer pattern, resulting in high contact resistance
Solution Approach 1:
A spacer is introduced as an intermediary structure surrounding the sidewall of the contact plug. This spacer acts as a mediator that enables the contact plug to contact the upper conductive layer pattern even when direct exposure is difficult, thereby resolving the contradiction between high integration and contact hole formation precision
Solution Approach 2:
The solution transitions from a two-dimensional contact hole approach to a three-dimensional contact structure with a spacer surrounding the sidewall. This dimensional change allows the contact plug to reach the upper conductive layer pattern through lateral support, overcoming the limitations of thin conductive layers in highly integrated devices
2Productivity
If the conductive layer patterns are made thinner to achieve high integration, then the device capacity increases, but the contact resistance between the gate structure and the contact plug increases
Solution Approach 1:
The spacer serves as a mediator structure that provides lateral support and guidance for the contact plug, enabling reliable contact with the upper conductive layer pattern despite its thin thickness. This intermediary structure reduces contact resistance by ensuring proper alignment and contact area
Solution Approach 2:
The invention changes the geometric parameters of the contact structure by introducing a spacer with specific dimensions that surround the contact plug sidewall. This parameter change enables the contact plug to effectively reach and contact the thin upper conductive layer pattern, thereby reducing contact resistance while maintaining high integration
Data Source
AI summary
A memory device includes a gate structure, a contact plug, and a spacer. The gate structure includes first and second conductive layer patterns sequentially stacked on a substrate. The contact plug passes through the second conductive layer pattern, and a sidewall of the contact plug directly contacts at least a portion of the second conductive layer pattern. The spacer surrounds a portion of the sidewall of the contact plug and contacting the gate structure.